We propose a methodology to determine the contents of a power efficient library: a set of sizes (drives) and beta ratios (pMOS widths divided by nMOS widths) that will enable a designer to achieve the best power versus delay tradeoff. The methodology utilizes an optimum continuous gate sizing tool. The software is not only able to produce the optimum continuous power-delay trade-off curve but also perform near optimum discrete gate selection from a given point on the continuous curve. Our results suggest that size options 0.5X, 1X, 2X, 3X, 4X and 3–4 beta ratios centered on the optimum delay beta is the least complex library than can generate power efficient designs. The reduced library yields a performance loss less than 1.5% compared to a much larger library with finer granularity in sizes and betas.
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