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首页> 外文会议>Proceedings of the 2009 IEEE Dallas Circuits and Systems Workshop >Elimination of spurious noise due to time-to-digital converter
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Elimination of spurious noise due to time-to-digital converter

机译：消除了由时间数字转换器引起的杂散噪声

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摘要

We propose an improved architecture of a multi-GHz all-digital phase-locked loop (ADPLL) that is free from spurious tones caused by the finite resolution of the phase detection process. These tones appear at the RF output when the synthesized frequency is very close to the integer-N multiple of the reference frequency. The phase detection in the ADPLL is performed by a time-to-digital converter (TDC), whose typical resolution of 10–30 ps is sufficient for the GSM-quality RF operation. While the TDC quantization noise does not normally produce significant phase noise degradation, the near-integer-N condition makes the loop ill-behaved such that the total quantization energy falls close to dc and will not get filtered by the loop filter. The proposed solution of randomizing the TDC quantization noise is verified through comprehensive and detailed simulations.
机译：我们提出了一种改进的多GHz全数字锁相环（ADPLL）架构，该架构不包含由相位检测过程的有限分辨率引起的杂音。当合成频率非常接近参考频率的整数N倍时，这些音调会出现在RF输出上。 ADPLL中的相位检测由一个时间数字转换器（TDC）执行，其典型分辨率为10–30 ps，足以实现GSM质量的RF工作。虽然TDC量化噪声通常不会产生明显的相位噪声降级，但接近整数N的条件会使环路表现不佳，从而使总量化能量接近dc，并且不会被环路滤波器滤波。通过全面而详细的仿真，验证了所提出的将TDC量化噪声随机化的解决方案。

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