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首页> 外文会议>Proceedings of the 2009 IEEE Dallas Circuits and Systems Workshop >Impact of context dependenent variability in CMOS embedded with SiGe on circuit performance power
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Impact of context dependenent variability in CMOS embedded with SiGe on circuit performance power

机译：嵌入SiGe的CMOS中上下文相关的可变性对电路性能和功耗的影响

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摘要

For CMOS circuits, the increase in power consumption has been curtailed in recent years by introducing mechanical stress to achieve device speed gain over and above the traditional speed vs. power tradeoffs achieved only by scaling gate lengths. Starting with the 90nm silicon node, induced compressive stress by embedded SiGe is being used to increase the hole mobility in PMOS. Because of the context dependence of this stress, local variability of the device parameters is expected to increase with this process method. In this paper, we discuss a method of direct measurement of the channel stress using Synchrotron X-ray diffraction and show the impact of resulting increased mobility and increased local variation on the circuit performance using Monte Carlo SPICE simulations of CMOS invertor based as well as NAND based ring oscillators. Simulation results demonstrate how lower supply voltage can be used to meet performance targets with lower power consumption.
机译：对于CMOS电路，近年来通过引入机械应力来实现器件速度增益的提高（已超过仅通过缩放栅极长度来实现的传统速度与功率的权衡），从而抑制了功耗的增加。从90nm硅节点开始，嵌入式SiGe引起的压应力被用于增加PMOS中的空穴迁移率。由于此压力的上下文相关性，使用此处理方法预期会增加设备参数的局部可变性。在本文中，我们讨论了使用同步加速器X射线衍射直接测量沟道应力的方法，并使用基于CMOS反相器和NAND的Monte Carlo SPICE仿真显示了增加的迁移率和增加的局部变化对电路性能的影响基于环形振荡器。仿真结果证明了如何使用较低的电源电压来满足具有较低功耗的性能目标。

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