A feasibility study of high-frequency buck regulators in nanometer CMOS technologies

机译：纳米CMOS技术中高频降压稳压器的可行性研究

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The feasibility of implementing buck converters with switching frequencies of 200MHz and beyond to reduce the size of passive components to integrate-able levels is investigated. Switching losses at such high frequencies are compared to traditional converters implemented on typical analog power technologies to demonstrate that the scaling down of CMOS technologies to nanometer levels can indeed enable switching at such high frequencies while maintaining decent efficiency. Preliminary simulation results on a typical 45nm technology are used to verify the feasibility.

机译：研究了采用200MHz及更高开关频率的降压转换器以将无源元件的尺寸减小到可集成水平的可行性。将这种高频下的开关损耗与在典型模拟功率技术上实现的传统转换器进行比较，以证明将CMOS技术缩小至纳米级确实可以在保持较高效率的同时在这种高频下进行开关。在典型的45nm技术上的初步仿真结果用于验证可行性。

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来源
《Proceedings of the 2009 IEEE Dallas Circuits and Systems Workshop》|2009年|p.1-4|共4页
会议地点 Richardson TX(US);Richardson TX(US)
作者
Fu Wei; Fayed Ayman;
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作者单位

Dept. of Electrical Computer Engineering, Iowa State University, Ames, Iowa;

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会议组织
原文格式 PDF
正文语种 eng
中图分类一般性问题;
关键词
Buck Converters; CMOS; DC-DC Converters;

机译：降压转换器; CMOS; DC-DC转换器;

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A feasibility study of high-frequency buck regulators in nanometer CMOS technologies

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