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Polychronous Analysis of Timing Constraints in UML MARTE

机译:UML MARTE中时间约束的多时性分析

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The UML Profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) defines a broadly expressive Time Model to provide a generic timed interpretation for UML models. As a part of MARTE, Clock Constraint Specification Language (CCSL) allows the specification of systems with multiple clock domains as well as nondeterminism. In this paper, we propose to take advantage of Polychrony clock calculus, named hierarchization, to analyze timed systems specified in CCSL, and to generate code for simulation considering determinism. Hierarchization enables to identify the endochrony property in a system that allows code generation ensuring determinism. The presented work is being integrated into the TimeSquare environment dedicated to the simulation of MARTE timed systems.
机译:用于实时和嵌入式系统建模和分析的UML概要文件(MARTE)定义了广泛表达的时间模型,为UML模型提供了通用的时间解释。作为MARTE的一部分,时钟约束规范语言(CCSL)允许规范具有多个时钟域以及不确定性的系统。在本文中,我们建议利用称为分层的多级时钟微积分技术来分析CCSL中指定的定时系统,并生成考虑确定性的仿真代码。通过分层,可以识别系统中的内同步属性,该系统允许代码生成确保确定性。提出的工作被集成到TimeSquare环境中,专门用于模拟MARTE定时系统。

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