• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>Proceedings of the 2010 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops (ISORC Workshops 2010) >Towards a Time-Predictable Hierarchical Memory Architecture - Prefetching Options to be Explored
【24h】

Towards a Time-Predictable Hierarchical Memory Architecture - Prefetching Options to be Explored

机译：迈向时间可预测的分层内存体系结构-将探索预取选项

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

In this paper we explore a hierarchical memory architecture that simplifies the WCET prediction of tasks. Instead of using cache memories for speeding up code execution, we propose to use hierarchical memories that are similar to scratchpad memories. These memories are filled by explicit prefetch operations that are executed in synchrony with program execution. The instructions respectively the data that determine both the content and the timing of the operations that perform the memory transfers between the different memory levels are computed at code-generation time. The paper describes the overall system and memory architecture, and design choices for explicitly controlled time-predictable hierarchical memory architectures.
机译：在本文中，我们探索了一种简化了任务的WCET预测的分层内存体系结构。我们建议不要使用类似于暂存器的分层存储器，而不是使用高速缓存来加快代码执行速度。这些存储器由与程序执行同步执行的显式预取操作填充。在代码生成时分别计算指令，这些数据确定内容和执行不同内存级别之间的内存转移的操作的时序。本文介绍了整个系统和内存架构，以及明确控制时间可预测的分层内存架构的设计选择。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号