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首页> 外文会议>Proceedings of the 2016 IEEE International Conference on Wireless Communications, Signal Processing and Networking >An efficient FPGA and KBNN based training and classification system for the implementation of VLSI architecture
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An efficient FPGA and KBNN based training and classification system for the implementation of VLSI architecture

机译：一个基于FPGA和KBNN的高效培训和分类系统，用于实现VLSI架构

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摘要

The Field Programmable Gate Array (FPGA) technology is widely used in various applications such as Digital Image Processing (DIP), Digital Signal Processing (DSP), data processing, etc. As the active and the passive components are fabricated in a single chip the performance level of the applications, the overall speed, area, and power of the application systems can be minimized effectively. The identification of the circuit information is an important process in the Very Large Scale Integration (VLSI) design. The existing architectures such as neural network, and brute force approach, etc., improve the analytical model work and refine the model using the trial and error method. The use of these existing techniques for the circuit information identification is inefficient, inaccurate, highly complex, time consuming, power consuming, and produced minimal classification result quality. To address these issues we have proposed a FPGA based VLSI architecture. The proposed architecture collects the feature values of the circuit manually. The collected features are then applied the Discrete Fourier Transform (DFT) based feature extraction process for identifying the information for the required data base and the input selected circuit details. The classification process is performed using the Knowledge Based Neural Network (KBNN). The performance of the proposed architecture is compared with the existing neural network methodology. The comparison results show that the suggested architecture increases the speed, reduces the overall power consumption, overall delay time, and also improves the circuit details classification speed level.
机译：现场可编程门阵列（FPGA）技术广泛用于各种应用中，例如数字图像处理（DIP），数字信号处理（DSP），数据处理等。由于有源和无源组件都在单个芯片中制造，因此，应用程序的性能级别，应用程序系统的整体速度，面积和功能可以有效地最小化。电路信息的识别是超大规模集成电路（VLSI）设计中的重要过程。现有的体系结构（例如神经网络和蛮力方法等）改进了分析模型的工作，并使用试错法改进了模型。这些现有技术用于电路信息识别的效率低下，不准确，高度复杂，耗时，耗电并且产生的分类结果质量极小。为了解决这些问题，我们提出了一种基于FPGA的VLSI架构。所提出的体系结构手动收集电路的特征值。然后，将所收集的特征应用于基于离散傅立叶变换（DFT）的特征提取过程，以识别所需数据库的信息和输入的所选电路详细信息。使用基于知识的神经网络（KBNN）执行分类过程。所提出的架构的性能与现有的神经网络方法进行了比较。比较结果表明，所建议的体系结构提高了速度，降低了总功耗，总延迟时间，并提高了电路细节分类的速度水平。

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