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首页> 外文会议>Proceedings of the 27th European solid-state device research conference >Building In Reliability with Latch-up, ESD and HOT Carrier Effects on a 0.25#Mu#M CMOS Technology
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Building In Reliability with Latch-up, ESD and HOT Carrier Effects on a 0.25#Mu#M CMOS Technology

机译：在0.25＃Mu＃M CMOS技术上通过闩锁，ESD和HOT载流子效应增强可靠性

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摘要

In this study, three major reliability aspects, hot carrier effects, latch-up and Electrostatic Discharge(ESD) have been simultaneously studied on a 0.25#mu#m CMOS technology. For the purpose, three source-drain archietectures processed on different kinds of substrate were compared with respect to these three reliability aspects. This work clearly demonstrates the dependence existing between them. The source-drai narchitecture affects of course the hot carrier reliability but also the ESD performances. A thinner epitaxial substrate is effective to reduce latch-up occurrence, but degrades the ESD failure threshold.
机译：在这项研究中，在0.25＃μ＃m CMOS技术上同时研究了三个主要可靠性方面，即热载流子效应，闩锁和静电放电（ESD）。为此，针对这三个可靠性方面，比较了在不同种类的基板上处理的三个源漏结构。这项工作清楚地表明了它们之间存在的依赖性。源-接地架构当然会影响热载流子的可靠性，但也会影响ESD性能。较薄的外延基板可有效减少闩锁现象，但会降低ESD故障阈值。

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