A synchronous wrapper for high-speed heterogeneous systems on FPGAs

机译：FPGA上的高速异构系统的同步包装器

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摘要

Taking advantage of synchronous and asynchronous paradigms, a new style of design, called Globally Synchronous Locally Asynchronous (GSLA), has achieved very interesting results. In this paper, we propose a synchronous wrapper that allows the communication of “synchronous to asynchronous to synchronous” modules. Internally, the proposed interface comprises an asynchronous module. The GSLA design style is interesting for Field-Programmable Gate Array (FPGA) platforms because it facilitates the design of Application Specific Integrated Circuits (ASIC). Through two case studies, the “differential equation solver” and the “FIR Filter”, we show that the proposed synchronous wrapper presents a reduction of up to 27% in the processing time and an increase of up to 747% in the global clock rate when compared with the synchronous design.

机译：利用同步和异步范式，一种称为全局同步本地异步（GSLA）的新型设计已取得了非常有趣的结果。在本文中，我们提出了一种同步包装器，该包装器允许“同步到异步再到同步”模块的通信。在内部，建议的接口包括一个异步模块。 GSLA设计风格对于现场可编程门阵列（FPGA）平台很有趣，因为它有助于专用集成电路（ASIC）的设计。通过“微分方程求解器”和“ FIR滤波器”两个案例研究，我们表明，所提出的同步包装器在处理时间方面最多减少了27％，在全局时钟速率下最多增加了747％。与同步设计相比。

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来源
《Proceedings of the 2016 IEEE ANDESCON》|2016年|1-4|共4页
会议地点 Arequipa(PE)
作者
Duarte L. Oliveira; Kledermon Garcia; Lester A. Faria; João Luis V. Oliveira; Leonardo Romano;
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作者单位

Electronic Engineer Divison - Technological Institute of Aeronautics - ITA - SJC, SP, Brazil;

Electronic Engineer Divison - Technological Institute of Aeronautics - ITA - SJC, SP, Brazil;

Electronic Engineer Divison - Technological Institute of Aeronautics - ITA - SJC, SP, Brazil;

Intitute Eldorado - Campinas, SP, Brazil;

Electric Engineer Department - University Center of FEI - SBC, SP, Brazil;

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原文格式 PDF
正文语种 eng
中图分类
关键词
Clocks; Field programmable gate arrays; Finite impulse response filters; Ports (Computers); Pipelines; Application specific integrated circuits; Very large scale integration;

机译：时钟;现场可编程门阵列;有限脉冲响应滤波器;端口（计算机）;管道;专用集成电路;超大规模集成;

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1. A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs [J] . MICHAEL PELLAUER, MURALIDARAN VIJAYARAGHAVAN, MICHAEL ADLER, ACM transactions on reconfigurable technology and systems . 2009,第3期

机译：A端口网络：保留用于在FPGA上建模的同步系统的定时行为
2. On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems [J] . Amirreza Yousefzadeh, Mirosław Jabłoński, Taras Iakymchuk, IEEE transactions on biomedical circuits and systems . 2017,第5期

机译：用于可扩展神经形态系统的商用FPGA上具有流控制和时钟校正功能的高速位串行双向LVDS链路上的多个AER握手通道
3. Design of Decoupled Wrapper for Globally Asynchronous Locally Synchronous Systems [J] . Myeong-Hoon OH, Seok-Jae PARK, Dong-Ik LEE, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences . 2004,第6期

机译：全局异步局部同步系统的解耦包装器设计
4. A synchronous wrapper for high-speed heterogeneous systems on FPGAs [C] . Duarte L. Oliveira, Kledermon Garcia, Lester A. Faria, IEEE ANDESCON Conference . 2016

机译：用于FPGA上的高速异构系统的同步包装器
5. Managing Temperature and Performance of FPGAs in Heterogeneous High-Performance Computing Systems [D] . Luo, Yingyi. 2020

机译：在异构高性能计算系统中管理FPGA的温度和性能
6. Real-Time FPGA Processing for High-Speed Optical Frequency Domain Imaging [O] . Adrien E. Desjardins, Benjamin J. Vakoc, Melissa J. Suter, -1

机译：实时FpGa处理高速光频域成像
7. On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems [O] . Yousefzadeh, Amirreza, Jabłonski, M., Iakymchuk, T., 2017

机译：用于可扩展神经形态系统的商用FPGA上具有流控制和时钟校正功能的高速位串行双向LVDS链路上的多个AER握手通道

A synchronous wrapper for high-speed heterogeneous systems on FPGAs

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