Synthesis tool for automatic layout generation of analog structures

机译：用于自动生成模拟结构布局的综合工具

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摘要

In this paper, a novel analog layout synthesis tool is presented. It is focused on two common analog building blocks: differential pairs and arrays of stacked devices. Starting from a circuit netlist and the names of the selected transistors, the tool verifies that these form a valid block and creates the corresponding layout. The user can define different layout parameters and the layout view can be generated with different levels of detail. Multiple layout views of a differential pair are generated to show its effectiveness to speed up the design process.

机译：本文提出了一种新颖的模拟布局综合工具。它着重于两个常见的模拟构建块：差分对和堆叠式设备阵列。该工具从电路网表和所选晶体管的名称开始，验证它们是否形成有效块并创建相应的布局。用户可以定义不同的布局参数，并且可以以不同的详细程度生成布局视图。生成差分对的多个布局图以显示其对加快设计过程的有效性。

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来源
《Proceedings of the 2016 IEEE ANDESCON》|2016年|1-4|共4页
会议地点 Arequipa(PE)
作者
Ismael Lomeli-Illescas; Sergio A. Solis-Bustos; Víctor H. Martínez-Sánchez; José E. Rayas-Sánchez;
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作者单位

Intel Corp., Zapopan, Jalisco, 45019 México;

Intel Corp., Zapopan, Jalisco, 45019 México;

Intel Corp., Zapopan, Jalisco, 45019 México;

Department of Electronics, Systems, and Informatics, ITESO - The Jesuit University of Guadalajara, Tlaquepaque, Jalisco, 45604 Mexico;

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会议组织
原文格式 PDF
正文语种 eng
中图分类
关键词
Layout; Transistors; Topology; Metals; Generators; Graphical user interfaces; Fingers;

机译：布局;晶体管;拓扑;金属;发电机;图形用户界面;手指;

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专利

1. A tool for the automatic generation and analysis of regular analog layout modules [J] . Lomeli-Illescas Ismael, Solis-Bustos Sergio A., Rayas-Sanchez Jose E. Integration . 2019,第MARa期

机译：自动生成和分析常规模拟布局模块的工具
2. A tool for the automatic generation and analysis of regular analog layout modules [J] . Lomeli-Illescas Ismael, Solis-Bustos Sergio A., Rayas-Sanchez Jose E. Integration . 2019,第Mara期

机译：用于自动生成和分析常规模拟布局模块的工具
3. LAYGEN II—Automatic Layout Generation of Analog Integrated Circuits [J] . Martins R., Lourenco N., Horta N. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2013,第11期

机译：LAYGEN II-模拟集成电路的自动布局生成
4. Synthesis tool for automatic layout generation of analog structures [C] . Ismael Lomeli-Illescas, Sergio A. Solis-Bustos, Víctor H. Martínez-Sánchez, IEEE ANDESCON Conference . 2016

机译：用于自动布局产生模拟结构的合成工具
5. Analog/RF VLSI layout generation: Layout retargeting via symbolic template. [D] . Jangkrajarng, Nuttorn. 2006

机译：模拟/ RF VLSI布局生成：通过符号模板重新布局。
6. IRSS: a web-based tool for automatic layout and analysis of IRES secondary structure prediction and searching system in silico [O] . Tzong-Yuan Wu, Chi-Chun Hsieh, Jun-Jie Hong, 2009

机译：IRSS：一种基于Web的工具可在计算机上自动布局和分析IRES二级结构预测和搜索系统
7. Automatic Stress Effects Computation Based On A Layout Generation Tool For Analog IC [O] . Youssef, Stéphanie, Dupuis, Damien, Iskander, Ramy, 2010

机译：基于布局生成工具的模拟IC自动应力效应计算

Synthesis tool for automatic layout generation of analog structures

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