FACTORS INFLUENCING THE THRESHOLD VOLTAGES OF METAL OXIDE CMOS DEVICES

机译：影响金属氧化物CMOS器件阈值电压的因素

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Scaling MOSFETs to improve performance results in higher gate leakage as the silicon dioxide gate dielectric becomes thinner. Furthermore, polysilicon depletion becomes a significant portion of the gate capacitance and limits the scalability of the overall capacitance. To address these issues, there has been much interest in replacing the silicon dioxide with a higher permittivity dielectric and the polysilicon with a metal gate electrode. Unfortunately, new materials can cause significant threshold voltage shifts that are unacceptable for CMOS devices. In this paper, we review the factors influencing the threshold voltages and discuss options for addressing the threshold voltage shifts.

机译：缩放MOSFET以提高性能会导致更高的栅极泄漏，因为二氧化硅栅极电介质变得更薄。此外，多晶硅耗尽成为栅极电容的重要部分，并限制了整个电容的可扩展性。为了解决这些问题，引起了很大的兴趣，是用较高介电常数的电介质代替二氧化硅，而用金属栅电极代替多晶硅。不幸的是，新材料可能导致CMOS器件无法接受的明显阈值电压漂移。在本文中，我们回顾了影响阈值电压的因素，并讨论了解决阈值电压漂移的选项。

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《Proceedings vol.2004-01; International Symposium on Advanced Short-Time Thermal Processing for Si-Based CMOS Devices II; 20040510-12; San Antonio,TX(US)》|2004年|P.313-320|共8页
会议地点 San AntonioTX(US)
作者
Christopher Hobbs; Leonardo Fonseca; Sri Samavedam; John Grant; Veer Dhandapani; Bill Taylor; LuRae Dip; Dina Triyoso; David Gilmer; Jamie Schaeffer; Rama Hegde; Hsing Tseng; Bruce White; Phil Tobin;
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Advanced Modules Group, Motorola, Crolles, France 38926;

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正文语种 eng
中图分类半导体技术;
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FACTORS INFLUENCING THE THRESHOLD VOLTAGES OF METAL OXIDE CMOS DEVICES

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