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首页> 外文会议>Proceedings vol.2004-01; International Symposium on Advanced Short-Time Thermal Processing for Si-Based CMOS Devices II; 20040510-12; San Antonio,TX(US) >OPTIMIZATION OF PRE-AMORPHIZATION AND DOPANT IMPLANT CONDITIONS FOR ADVANCED ANNEALING
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OPTIMIZATION OF PRE-AMORPHIZATION AND DOPANT IMPLANT CONDITIONS FOR ADVANCED ANNEALING

机译：先进退火的预非晶化和掺杂剂注入条件的优化

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摘要

As CMOS device dimensions shrink toward the 45 nm technology node, the junction depth of the source/drain extensions must decrease to 7-12 nm in order to minimize short channel effects. Simultaneously, the desire for high transistor drive currents and fast device performance leads to the requirement of a maximum PMOS extension sheet resistance of 830 Ω/□. In order to meet the junction depth requirement, advanced annealing techniques with maximum temperature dwell times of about one millisecond are being developed and assessed, since they enable dopant activation with minimal diffusion from the as-implanted dopant profile. Nevertheless, achieving low sheet resistances with junctions formed by these advanced anneals is a challenge. Pre-amorphization with Ge~+ ions is commonly used to reduce the as-implanted junction depth by minimizing channeling, but the pre-amorphization implant conditions influence the junction sheet resistance along with the dopant implant conditions. This paper will discuss an optimization study of pre-amorphization and dopant implant conditions with advanced annealing for PMOS source/drain extension formation. Ge~+ pre-amorphization implant energy and dose and the dose of 0.5 keV B~+ dopant implants were varied to find the minimum sheet resistance. The optimal implant conditions for advanced anneal are found to be different from those previously reported for spike anneal. Two types of dopant activation mechanisms will be discussed to explain the different sets of optimum conditions.
机译：随着CMOS器件尺寸向45 nm技术节点缩小，源极/漏极扩展的结深度必须减小至7-12 nm，以最大程度地减小短沟道效应。同时，对高晶体管驱动电流和快速器件性能的需求导致要求最大PMOS扩展薄层电阻为830Ω/□。为了满足结深度要求，正在开发和评估具有大约一毫秒最大温度停留时间的先进退火技术，因为它们能够实现掺杂物活化，并且从植入时的掺杂物分布中扩散最小。然而，通过这些高级退火形成的结实现低薄层电阻是一个挑战。通常使用Ge〜+离子进行预非晶化以通过最小化沟道来减小注入时的结深度，但是预非晶化注入条件会影响结薄层电阻以及掺杂剂注入条件。本文将讨论通过高级退火对PMOS源/漏扩展层形成进行预非晶化和掺杂注入条件的优化研究。改变Ge〜+预非晶化注入的能量和剂量以及0.5keV B〜+掺杂剂的剂量，以求出最小的薄层电阻。发现用于高级退火的最佳植入条件与先前报道的尖峰退火的条件不同。将讨论两种类型的掺杂剂激活机制来解释最佳条件的不同集合。

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