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首页> 外文会议>Proceedings vol.2004-13; International Symposium on Nanoscale Devices, Materials, and Biological Systems: Fundamentals and Applications; ; >Design and Implementation of Ultra-Small-Size and Ultra-Low-Power Digital Systems on GaAs-based Hexagonal Nanowire Networks Utilizing a Hexagonal BDD Quantum Circuit Approach
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Design and Implementation of Ultra-Small-Size and Ultra-Low-Power Digital Systems on GaAs-based Hexagonal Nanowire Networks Utilizing a Hexagonal BDD Quantum Circuit Approach

机译：基于六角形BDD量子电路方法的基于GaAs的六角形纳米线网络上的超小型和超低功耗数字系统的设计与实现

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摘要

This paper discusses feasibility of design and future implementation of ultra-small-size and ultra-low-power digital logic systems by a hexagonal BDD (binary-decision diagram) quantum circuit approach. The discussion is based on various circuits formed on GaAs-based hexagonal nanowire networks controlled by nanometer scale Schottky wrap gates (WPGs). Starting from basic node devices and elementary logic function blocks, fabrication technology of hexagonal BDD quantum circuits up to 8-bit adders with node densities over 45 million nodes/cm~2 has been successfully developed. Their correct operations at low temperatures and room temperature have been confirmed by experiments and simulation. Various circuit components in logic processors, including arithmetic logic unit (ALU), controller and decoders have been successfully designed as hexagonal BDD layouts without nanowire crossover. For sequential circuits, WPG-controlled nanowire FETs on hexagonal networks have been investigated, and registers and counters have been implemented using these nanowire FETs showing correct operation. Hexagonal BDD-based static 2-bit nano-processor unit (NPU) has been successfully designed completely on hexagonal nanowire network. Ultra high-density GaAs hexagonal nanowire networks with much smaller wire sizes than those of etched nanowire networks have been successfully formed by selective MBE growth, showing great promise for room temperature operation in quantum regime as well as reduction of system area and power consumption.
机译：本文讨论了利用六角形BDD（二进制决策图）量子电路方法设计超小型和超低功耗数字逻辑系统的可行性和未来的实现。讨论基于在纳米级肖特基环绕栅（WPG）控制的基于GaAs的六角形纳米线网络上形成的各种电路。从基本节点设备和基本逻辑功能块开始，已经成功地开发了六边形BDD量子电路的制造技术，其节点密度超过4500万个节点/ cm〜2的8位加法器。通过实验和仿真已经证实了它们在低温和室温下的正确运行。逻辑处理器中的各种电路组件（包括算术逻辑单元（ALU），控制器和解码器）已成功设计为六方BDD布局，而没有纳米线交叉。对于顺序电路，已经研究了六边形网络上WPG控制的纳米线FET，并已使用显示正确操作的这些纳米线FET实现了寄存器和计数器。基于六角BDD的静态2位纳米处理器单元（NPU）已成功地完全设计在六角纳米线网络上。通过选择性的MBE生长，成功地形成了线尺寸比蚀刻的纳米线网络小得多的超高密度GaAs六角形纳米线网络，这显示了在量子状态下室温操作以及减少系统面积和功耗的巨大希望。

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