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首页> 外文会议>Proceedings vol.2005-08; International Symposium on Microelectronics Technology and Devices(SBMICRO 2005); 200509; >DEFECT ENGINEERING IN HIGH-MOBILITY SUBSTRATES FOR ADVANCED CMOS TECHNOLOGIES
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DEFECT ENGINEERING IN HIGH-MOBILITY SUBSTRATES FOR ADVANCED CMOS TECHNOLOGIES

机译：先进CMOS技术的高移动性基材中的缺陷工程

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摘要

The scaling trend in accordance with the ITRS roadmap put some stringent requirements on the device mobility, especially for sub 45 nm technology nodes. Although the implementation of FUSI and/or metal gate electrodes can reduce the mobility degradation associated with the use of high-k dielectrics, much attention is nowadays given to the use of so-called high mobility substrates. This paper reviews key aspects of defect control and defect engineering in high mobility substrates, such as strained Si, SiGe, Ge and GeOI, to be used for advanced CMOS technologies. Focus will be on defect generation and its impact on the electrical device performance parameters. The global or local strain engineering has to be optimized in order to avoid the harmful effects of stress-induced misfit and threading dislocations.
机译：符合ITRS路线图的扩展趋势对设备移动性提出了一些严格要求，尤其是对于45纳米以下技术节点。尽管FUSI和/或金属栅电极的实施可以减少与使用高k电介质相关的迁移率降低，但是如今，人们对使用所谓的高迁移率衬底给予了极大的关注。本文概述了用于高CMOS技术的高迁移率衬底（如应变Si，SiGe，Ge和GeOI）中缺陷控制和缺陷工程的关键方面。重点将放在缺陷的产生及其对电子设备性能参数的影响上。为了避免应力引起的不匹配和螺纹错位的有害影响，必须对全局或局部应变工程进行优化。

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