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首页> 外文会议>Proceedings vol.2005-08; International Symposium on Microelectronics Technology and Devices(SBMICRO 2005); 200509; >MORPHOLOGICAL AND ELECTRICAL STUDY OF POLY-SiGe ALLOY DEPOSITED BY VERTICAL LPCVD
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MORPHOLOGICAL AND ELECTRICAL STUDY OF POLY-SiGe ALLOY DEPOSITED BY VERTICAL LPCVD

机译：垂直LPCVD沉积的Si-SiGe合金的形貌和电学研究

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摘要

In this paper authors report morphological and deposition analysis of poly-SiGe thin films by means of AFM, SEM and Raman measurements and electrical characteristics of MOS capacitors using poly-SiGe electrodes. The samples were deposited in a pancake vertical LPCVD system using Silane and Germane as precursor gases in a Hydrogen carrier flow. The process pressure was 5 or 10 Torr, in a temperature range from 500 ℃ to 750 ℃. Surface RMS roughness, grain size and deposition rate are evaluated. We found that very uniform films can be obtained, with rms roughness below 4 nm and grain size below 50 nm. Deposition rates as high as 1500 A/min are achieved. The deposited samples presented Rs values well bellow similar poly-Si films and electrical characterization shows poly-SiGe as a suitable material for MOS devices.
机译：在本文中，作者报告了通过AFM，SEM和拉曼测量以及使用聚SiGe电极的MOS电容器的电特性对聚SiGe薄膜进行形貌和沉积分析。将样品沉积在煎饼垂直LPCVD系统中，使用硅烷和锗烷作为氢气载流中的前体气体。在500℃至750℃的温度范围内，过程压力为5或10 Torr。评估表面RMS粗糙度，晶粒尺寸和沉积速率。我们发现可以获得非常均匀的薄膜，均方根粗糙度低于4 nm，晶粒尺寸低于50 nm。沉积速度高达1500 A / min。沉积的样品呈现出的Rs值非常接近类似的多晶硅膜，并且电学特性表明，多晶硅-GeGe是适合MOS器件的材料。

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