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首页> 外文会议>Sensor, Mesh and Ad Hoc Communications and Networks Workshops, 2009. SECON Workshops '09 >Reconfiguring Crypto Hardware Accelerators on Wireless Sensor Nodes
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Reconfiguring Crypto Hardware Accelerators on Wireless Sensor Nodes

机译：在无线传感器节点上重新配置加密硬件加速器

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Running strong cryptographic algorithms on wireless sensor nodes is extremely difficult due to their limited resources. Hardware accelerators are a suitable means t speed up the computation and reduce power consumption. The drawback of crypto ASICs is the loss of flexibility. In this paper we will shortly introduce a modular design of elliptic curve accelerators which allows to be adjusted to several NIST recommended curves be replacing its reduction unit. This partial reconfiguration will be executed on a Spartan 3 FPGA. The visualization will be done in the following way. Standard motes will be connected to the FPG. On the motes the algorithms will be executed in software. Switching between ECC with a long key i.e. 571 bit and those with short key length e.g. to a key length of 163 bit, has a remarkable effect on the execution time. En-/decrypting messages sent to and received from the motes at the FPGA will show that ECC implementation has been reconfigured according to the selected curve on the motes.
机译：由于其有限的资源，在无线传感器节点上运行强大的加密算法非常困难。硬件加速器是加快计算速度并降低功耗的合适方法。加密ASIC的缺点是缺乏灵活性。在本文中，我们将简短介绍椭圆曲线加速器的模块化设计，该椭圆加速器可以调整为多个NIST推荐的曲线，以替代其减速单元。此部分重新配置将在Spartan 3 FPGA上执行。可视化将通过以下方式完成。标准微粒将连接到FPG。在算法上，算法将在软件中执行。在具有长密钥（即571位）的ECC和具有短密钥长度（例如571位）的ECC之间切换密钥长度为163位，对执行时间有显着影响。在FPGA上发送到节点或从节点接收消息的加密/解密将表明，已根据节点上选定的曲线对ECC实现进行了重新配置。

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