A Simple Background Interstage Gain Calibration Technique for Pipeline ADCs

机译：管道ADC的简单背景级间增益校准技术

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摘要

The pipelined architecture is one of the most popular analog-to-digital converter (ADC) architectures. Various circuit nonidealities such as finite opamp gain and mismatch in capacitors limit the pipelined ADCpsilas performance. In this paper, a new technique for the calibration of interstage gain errors in pipelined ADCpsilas are described. The proposed calibration scheme uses a slow but accurate ADC as a reference ADC to determine the gain error of the stage under calibration in digital domain independent other stages. Then, correction of each stage error is done in analog domain. The calibration technique calibrates capacitor mismatch as well as finite opamp dc gain, while the digital redundancy compensates for comparator offset. Simulation shows that with this calibration scheme, SNDR improved from 39 dB to 72 dB for a 12-bit pipeline ADC.

机译：流水线架构是最流行的模数转换器（ADC）架构之一。各种电路非理想因素，例如有限的运算放大器增益和电容器中的失配，都会限制流水线ADCpsilas的性能。本文介绍了一种用于校准流水线ADCpsilas中级间增益误差的新技术。所提出的校准方案使用缓慢但准确的ADC作为参考ADC来确定独立于数字域的其他级中正在校准的级的增益误差。然后，在模拟域中完成每个阶段误差的校正。校准技术可校准电容器失配以及有限的运算放大器直流增益，而数字冗余可补偿比较器失调。仿真表明，采用这种校准方案，对于12位流水线ADC，SNDR从39 dB提高到72 dB。

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来源
《Signal Acquisition and Processing, 2009. ICSAP 2009》|2009年|221-224|共4页
会议地点 Kuala Lumpur(MY);Kuala Lumpur(MY)
作者
Tahmasebi A.; Kamali A.; Kanani Z.D.K.; Sobhi J.;
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Islamic Azad Univ. Sarab, Sarab, Iran;

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关键词
analogue-digital conversion; calibration; comparators (circuits); operational amplifiers; pipeline processing; redundancy; analog domain; analog-to-digital converter; capacitor mismatch; circuit nonidealities; comparator offset; dc gain; digital redundancy; finite opamp; interstage gain errors; pipelined architecture; word length 12 bit; Analog-to-digital converter (ADC); Pipeline; Reference ADC; Stage gain;

机译：模数转换;校准;比较器（电路）;运算放大器;流水线处理;冗余;模拟域;模数转换器;电容器失配;电路非理想性;比较器失调;直流增益;数字冗余;有限运放;级间增益错误;流水线架构;字长12位;模数转换器（ADC）;管道;参考ADC;级增益;

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专利

1. Background interstage gain calibration technique for pipelined ADCs [J] . Keane J.P., Hurst P.J., Lewis S.H. IEEE transactions on circuits and systems . I , Regular papers . 2005,第1期

机译：流水线ADC的后台级间增益校准技术
2. Background Interstage Gain Calibration Technique for Pipelined ADCs [J] . John P. Keane, Paul J. Hurst, Stephen H. Lewis IEEE Transactions on Circuits and Systems. 1, Fundamental Theory and Applications . 2005,第1期

机译：流水线ADC的后台级间增益校准技术
3. A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration [J] . Dadian Zhou, Carlos Briseno-Vidrios, Junning Jiang, IEEE transactions on circuits and systems . I , Regular papers . 2019,第9期

机译：使用电流重用技术以及级间增益和非线性误差校准的13位260MS / s高效管线ADC
4. A simple background interstage gain calibration technique for pipeline ADCs [C] . Sobhi J., Kanani Z.K., Tahmasebi A., International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology;ECTI-CON 2009 . 2009

机译：用于流水线ADC的简单背景级间增益校准技术
5. Background digital calibration for interstage gain errors and memory effects in pipelined analog-to-digital converters. [D] . Keane, John Patrick. 2004

机译：用于流水线模数转换器中级间增益误差和存储效应的背景数字校准。
6. Histogram-Based Calibration Method for Pipeline ADCs [O] . Hyeonuk Son, Jaewon Jang, Heetae Kim, -1

机译：基于直方图的管道ADC校准方法
7. Convergence Analysis of a Background Interstage Gain Calibration Technique for Pipelined ADCs* [O] . Dong Wang, John P. Keane, Paul J. Hurst, 2008

机译：用于流水线ADC的后台级间增益校准技术的收敛性分析*

A Simple Background Interstage Gain Calibration Technique for Pipeline ADCs

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