Using Commercial Semiconductor Technologies in Space

机译：在太空中使用商用半导体技术

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New issues are discussed that must be considered when unhardened commercial technologies are used in space applications, as well as hardness assurance techniques. Large differences in dose-rate effects were observed for different circuit types from the same manufacturer, which may be due to differences in the thickness of isolation oxides used in processing. Data are presented for scaled MOS devices that show how total dose hardness and hard error rates are projected as devices are scaled to smaller feature size. Hard errors are expected to be a significant problem for devices with feature size below 0.6 μm.

机译：讨论了在空间应用中使用未硬化的商业技术以及硬度保证技术时必须考虑的新问题。对于来自同一制造商的不同电路类型，观察到剂量率效应差异很大，这可能是由于加工中使用的隔离氧化物厚度不同所致。给出了按比例缩放的MOS器件的数据，这些数据显示了随着器件按比例缩小到较小的特征尺寸时，如何投影总剂量硬度和硬错误率。对于特征尺寸小于0.6μm的器件，硬错误预计将是一个重大问题。

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《Third European conference on radiation and its effects on components and systems》|1995年|175-182|共8页
会议地点 Arcachon(FR);Arcachon(FR)
作者
A. H. Johnston; C. I. Lee; B. G. Rax; D. C. Shaw;
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作者单位

Jet Propulsion Laboratory California Institute of Technology Pasadena, California;

Jet Propulsion Laboratory California Institute of Technology Pasadena, California;

Jet Propulsion Laboratory California Institute of Technology Pasadena, California;

Jet Propulsion Laboratory California Institute of Technology Pasadena, California;

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正文语种 eng
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Using Commercial Semiconductor Technologies in Space

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