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首页> 外文会议>VLSI, 2009. ISVLSI '09 >High Performance Non-blocking Switch Design in 3D Die-Stacking Technology
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High Performance Non-blocking Switch Design in 3D Die-Stacking Technology

机译：3D叠层技术中的高性能无阻塞开关设计

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摘要

Die stacking is a promising new technology that enables integration of devices in the third dimension. It allows the stacking of multiple active layers directly on top of one another with short, dense die-to-die vias providing communication. Previous work has shown significant benefits at all design targets, from stacking memory on logic to partitioning individual architectural units across multiple layers. Many high-speed processor units-ALUs, register files, caches, and instruction schedulers-have all been designed in 3D, achieving significant, simultaneous power savings and performance boosts. Other work has looked at the implementation of network-on-chip in a die stack but restricted the focus to planar designs of the various unit(processors, routers, etc.). This work follows up on these two re-search areas to explore the 3D design of router components, specifically the crossbar. We examine the implementation of a crossbar and two multistage interconnect networks to determine the potential benefits of 3D implementations. Compared to equivalent planar designs,we achieve a maximum delay reduction of 26% and maximum power savings of 24%.
机译：裸片堆叠是一种有前途的新技术，可以在第三维集成器件。它允许通过短而密集的芯片对芯片过孔提供通信的方式，将多个有源层直接堆叠在一起。先前的工作已显示出所有设计目标的显着优势，从在逻辑上堆叠内存到在多层结构中划分单个架构单元。许多高速处理器单元-ALU，寄存器文件，高速缓存和指令调度器-均采用3D设计，可实现显着的同时节能和性能提升。其他工作着眼于在芯片堆叠中实现片上网络，但将重点局限于各种单元（处理器，路由器等）的平面设计。这项工作是针对这两个研究领域的，以探索路由器组件的3D设计，尤其是交叉开关。我们检查了交叉开关和两个多级互连网络的实现，以确定3D实现的潜在好处。与同等的平面设计相比，我们最大程度地减少了26％的延迟，最大节省了24％的功率。

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