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An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC

机译：一个8位1.8 V 500 MSPS CMOS分段电流控制DAC

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This paper presents design of an 8-bit 1.8 V segmented current steering (CS) digital-to-analog converter (DAC) using 0.18 mum double poly five metal CMOS technology. The DAC has been segmented as 6+2 to achieve optimum performance for minimum area. The simulation result shows a maximum DNL of 0.30 LSB and an INL of 0.33 LSB. The midcode glitch is 0.27 pV s. The simulated SNDR and SFDR of the segmented DAC are 52.13 dB and 44.83 dB respectively. The settling of the segmented DAC is 6.02 ns. The power consumption is simulated as 7.88 mW. The prototype will be used in telecommunication applications.

机译：本文介绍了一种采用0.18微米双多晶硅五金属CMOS技术的8位1.8 V分段电流控制（CS）数模转换器（DAC）的设计。 DAC被细分为6 + 2，以在最小面积上实现最佳性能。仿真结果显示最大DNL为0.30 LSB，INL为0.33 LSB。中间码毛刺为0.27 pV s。分段DAC的仿真SNDR和SFDR分别为52.13 dB和44.83 dB。分段DAC的建立时间为6.02 ns。功耗模拟为7.88 mW。该原型将用于电信应用。

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《VLSI, 2009. ISVLSI '09》|2009年|268-273|共6页
会议地点 Tampa FL(US);Tampa FL(US)
作者
Sarkar S.; Banerjee S.;
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作者单位

Dept. of Electron. Electr. Eng., Indian Inst. of Technol., Kharagpur;

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CMOS integrated circuits; digital-analogue conversion; logic design; current steering; digital-to-analog converter; double poly five metal CMOS technology; power 7.88 mW; power consumption; size 0.18 mum; voltage 0.27 pV; voltage 1.8 V; analog CMOS circuits; digital to analog conversion; low power; segmented current steering architecture;

机译：CMOS集成电路;数模转换;逻辑设计;电流控制;数模转换器;双多晶硅五金属CMOS技术;功率7.88 mW;功耗;尺寸0.18微米;电压0.27 pV;电压1.8 V;模拟CMOS电路;数模转换;低功耗;分段电流控制架构;

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1. AN 8-BIT 500MSPS CMOS A/D CONVERTER WITH A NOVEL ANALOG DYNAMIC LATCH [J] . Sanghoon Hwang, Minkyu Song 電子情報通信学会技術研究報告. シリコン材料·デバイス. Silicon Devices and Materials . 2004,第155期

机译：具有新型模拟动态锁存功能的8位500MSPS CMOS A / D转换器
2. AN 8-BIT 500MSPS CMOS A/D CONVERTER WITH A NOVEL ANALOG DYNAMIC LATCH [J] . Sanghoon Hwang, Minkyu Song 電子情報通信学会技術研究報告. 電子デバイス. Electron Devices . 2004,第152期

机译：具有新型模拟动态锁存功能的8位500MSPS CMOS A / D转换器
3. An 8-Bit Ultra-Low-Power, Low-Voltage Current Steering DAC Utilizing a New Segmented Structure [J] . Bandali Mehdi, Hassanzadeh Alireza, Ghashghaie Masoume, Journal of circuits, systems and computers . 2019,第10期

机译：利用新型分段结构的8位超低功耗，低压电流控制DAC
4. An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC [C] . Santanu Sarkar, Swapna Banerjee IEEE Computer Society Annual Symposium on VLSI . 2009

机译：8位1.8 V 500 MSPS CMOS分段电流转向DAC
5. Behavioral simulation of digital to analog converters simulation of segmented current steering DAC with utilization of perfect sampling technique. [D] . Warecki, Sylwester. 2002

机译：数模转换器的行为仿真，利用完美的采样技术对分段电流控制DAC进行仿真。
6. A CMOS Current Steering Neurostimulation Array with Integrated DAC Calibration and Charge Balancing [O] . Elliot Greenwald, Christoph Maier, Qihong Wang, -1

机译：具有集成DAC校准和电荷平衡的CMOS电流控制神经刺激阵列
7. Design of a 1.8V 8-bit 500MSPS Folding-Interpolation CMOS A/D Converter with a Folder Averaging Technique [O] . Lee, Dongjin, Song, Jaewon, Shin, Jongha, 2007

机译：采用折叠平均技术的1.8V 8位500msps折叠插值CmOs a / D转换器的设计

An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC

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