A low-jitter all-digital phase-locked loop using a suppressive digital loop filter

机译：使用抑制型数字环路滤波器的低抖动全数字锁相环

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摘要

In this paper we present a low-jitter and wide-range all-digital phase-locked loop (ADPLL). The digitally controlled oscillator (DCO) is able to operate from 53 to 560 MHz with 5.1 ps resolution. Combined with a programmable divider with multiplicative factor from 1 to 2046, various frequencies could be synthesized to meet different applications. In order to reduce output clock jitter after phase locking, we propose a three-step locking procedure. The phase can be locked quickly through a preliminary phase locking scheme and the jitter is then reduced by the proposed suppressive digital loop filter. Simulation results show the jitter performance is very close to that of free running DCO. The jitter_Pk-Pk and jitter_RMS is 51 ps and 6.74 ps respectively when the output clock of ADPLL operates at 200 Mhz.

机译：在本文中，我们提出了一种低抖动，宽范围的全数字锁相环（ADPLL）。数控振荡器（DCO）能够以5.1 ps的分辨率在53至560 MHz的频率下工作。结合具有1到2046的乘法因子的可编程分频器，可以合成各种频率以满足不同的应用。为了减少锁相后的输出时钟抖动，我们提出了一个三步锁定程序。可以通过初步的相位锁定方案快速锁定相位，然后通过提出的抑制性数字环路滤波器来降低抖动。仿真结果表明，抖动性能非常接近自由运行的DCO。当ADPLL的输出时钟工作在200 MHz时，抖动_{Pk-Pk 和抖动_{RMS 分别为51 ps和6.74 ps。}}

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《VLSI Design, Automation and Test, 2009. VLSI-DAT '09》|2009年|158-161|共4页
会议地点 Hsinchu(CT);Hsinchu(CT)
作者
Hsuan-Jung Hsu; Shi-Yu Huang;
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Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Hsinchu, Taiwan;

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digital phase locked loops; oscillators; all-digital phase-locked loop; digital loop filter; digitally controlled oscillator; frequency 200 MHz; frequency 53 MHz to 560 MHz; low-jitter phase-locked loop;

机译：数字锁相环;振荡器;全数字锁相环;数字环路滤波器;数控振荡器;频率200 MHz;频率53 MHz至560 MHz;低抖动锁相环;

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2. A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment [J] . Lin Jung-Mao, Yang Ching-Yuan Circuits and Systems I: Regular Papers, IEEE Transactions on . 2015,第10期

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3. A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy [J] . Kratyuk V., Hanumolu P.K., Un-Ku Moon, IEEE transactions on circuits and systems. II, Express briefs . 2007,第3期

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4. A Low-Jitter All-Digital Phase-Locked Loop Using a Suppressive Digital Loop Filter [C] . Hsuan-Jung Hsu, Shi-Yu Huang International Symposium on VLSI Design, Automation and Test . 2009

机译：使用抑制数字环路滤波器的低抖动全数字锁相环
5. Analysis and Hardening of All-digital Phase-locked Loops (ADPLLs) to Single-event Radiation Effects [D] . Chen, Yanran Paula 2017

机译：全数字锁相环（ADPLL）的分析和硬化对单事件辐射效应
6. An All-Digital Fast Tracking Switching Converter with a Programmable Order Loop Controller for Envelope Tracking RF Power Amplifiers [O] . Nijad Anabtawi, Rony Ferzli, Haidar M. Harmanani -1

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7. Application of multirate digital filter banks to wideband all-digital phase-locked loops design [O] . Shah, B., Sadr, R., Hinedi, S. 1992

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8. Application of multirate digital filter banks to wideband all-digital phase-locked loops design [R] . Sadr, R., Shah, B., Hinedi, S. 1992

机译：多速率数字滤波器组在宽带全数字锁相环设计中的应用

A low-jitter all-digital phase-locked loop using a suppressive digital loop filter

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