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首页> 外文会议>VLSI Design, Automation and Test, 2009. VLSI-DAT '09 >Rewired retiming for free flip-flop reductions without delay penalty
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Rewired retiming for free flip-flop reductions without delay penalty

机译：有线重新定时，可免费减少触发器，而不会增加延迟

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摘要

Due to the intrinsic difference between fan-in and fan-out counts of a retimed component, the number of flip-flops tends to be undesirably increased in a conventional retiming procedure, which can cause a significant area/power penalty on the retimed circuit. Nonetheless, because of the higher dominance on interconnect delays, without a mechanism to reflect real physical design accurately, the clock period produced by a retiming scheme will be unrealistic. To overcome these two major drawbacks of the conventional retiming technique, we propose a novel retiming flow combined with rewiring, being able to largely cut down flip-flops (FFs) while with the original retimed clock period uncompromised. For a more accurate delay estimation, all interconnect delays are formulated and calculated based on real placements. Experimental results show that this novel rewired retiming scheme can bring a reduction of 18.7% (on average) on the number of flip-flops compared to the original retiming without rewiring. This large FF reduction can be considered a free gain as the retimed clock period can still be kept without compromise in such flow. Further experiments have indicated that about 8.26% of the total dynamic power can be saved.
机译：由于重定时组件的扇入和扇出计数之间的固有差异，在常规的重定时过程中，触发器的数量往往会不希望地增加，这会在重定时电路上造成很大的面积/功耗损失。但是，由于在互连延迟方面占支配地位，而没有一种机制可以准确反映实际的物理设计，因此由重定时方案产生的时钟周期将是不现实的。为了克服常规重定时技术的这两个主要缺点，我们提出了一种与重布线相结合的新颖的重定时流程，能够在不影响原始重定时时钟周期的情况下大幅降低触发器（FF）。为了获得更准确的延迟估计，所有互连延迟都是根据实际布局制定和计算的。实验结果表明，与没有重新布线的原始重新时序相比，这种新颖的重新布线重新时序方案可以使触发器的数量平均减少18.7％。可以将这种大的FF减小视为自由增益，因为仍然可以在不影响这种流程的情况下保持重新计时的时钟周期。进一步的实验表明，可以节省总动能的8.26％。

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