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首页> 外文会议>VLSI Design (VLSID), 2012 25th International Conference on >Design for Security of Block Cipher S-Boxes to Resist Differential Power Attacks
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Design for Security of Block Cipher S-Boxes to Resist Differential Power Attacks

机译：分组密码S-Box抵抗差分功率攻击的安全性设计

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摘要

This paper proposes an S-box construction of AES-128 block cipher which is more robust to differential power analysis (DPA) attacks than that of AES-128 implemented with Rijndael S-box while having similar cryptographic properties. The proposed S-box avoids use of countermeasures for thwarting DPA attacks thus consuming lesser area and power in the embedded hardware and still being more DPA resistive compared to Rijndael S-box. The design has been prototyped on Xilinx FPGA Spartan device XC3S400-4PQ208 and the power traces of the two different running AES-128 algorithms with the proposed and Rijndael S-boxes have been analyzed separately. The experimental results of the FPGA implementations show a lesser gate count consumption and increased throughput for the AES-128 with proposed S-box as that when implemented with Rijndael S-box on the same FPGA device. The requirement of higher number of power traces to perform DPA analysis on AES-128 with RAIN S-box as compared to that implemented with Rijndael S-box is an experimental validation of the theoretical claim of lower transparency order computed for RAIN S-box as being more DPA resistant than that of Rijndael S-box.
机译：本文提出了一种AES-128分组密码的S-box结构，它比采用Rijndael S-box实现的AES-128具有更强的加密性能，同时对差分功率分析（DPA）攻击更健壮。与Rijndael S-box相比，建议的S-box避免了使用对付DPA攻击的对策，从而减少了嵌入式硬件的面积和功耗，并且对DPA的抵抗力更大。该设计已在Xilinx FPGA Spartan器件XC3S400-4PQ208上进行了原型设计，并分别分析了两种不同运行AES-128算法以及拟议中的S-box和Rijndael S-box的功率曲线。 FPGA实现的实验结果表明，与在同一FPGA器件上使用Rijndael S-box实现的AES-128和拟议的S-box相比，AES-128的门数消耗更少，吞吐量增加。与用Rijndael S-box实现的相比，在带有RAIN S-box的AES-128上对AES-128进行DPA分析需要更多的功率迹线，这是对RAIN S-box计算出的较低透明度顺序的理论要求的实验验证。比Rijndael S-box更耐DPA。

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