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HARDWARE IMPLEMENTATION OF CHINESE REMAINDER THEOREM USING REDUNDANT BINARY REPRESENTATION

机译：冗余二进制表示法对剩余定理的硬件实现

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摘要

In this paper, it is proposed that a new method for hardware implementation of CRT. Taking R.B representation, we can realize the CRT algorithm which needs only one stage CPA though the conventional methods use several stages of that. The proposed method can reduce the maximum delay of computing time in RNS-binary conversion.

机译：本文提出了一种新的CRT硬件实现方法。以R.B表示，我们可以实现仅需要一个阶段CPA的CRT算法，尽管传统方法使用了多个阶段。所提出的方法可以减少RNS二进制转换中计算时间的最大延迟。

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来源
《VLSI signal processing, VIII》|1995年|552-561|共10页
会议地点 Sakai(JP)
作者
Kazuhiro Ariyama; Hisamichi Toyoshima;
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作者单位

Department of Electrical Engineering Kanagawa University Yokohama, JAPAN;

Department of Electrical Engineering Kanagawa University Yokohama, JAPAN;

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会议组织
原文格式 PDF
正文语种 eng
中图分类微电子学、集成电路（IC）;通信理论;
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4. Hardware implementation of Chinese remainder theorem using redundant binary representation [C] . Ariyama, K., Toyoshima, . 1995

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5. Studies on Hardware Algorithms for Arithmetic Operations with a Redundant Binary Representation [D] . Takagi, Naofumi 1988

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HARDWARE IMPLEMENTATION OF CHINESE REMAINDER THEOREM USING REDUNDANT BINARY REPRESENTATION

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