首页> 外文会议>Wireless Technology >The Construction of Minimal Area Power and Ground Nets for VLSI Circuits

【24h】

The Construction of Minimal Area Power and Ground Nets for VLSI Circuits

机译：VLSI电路的最小面积电源和接地网的构建

获取原文

获取原文并翻译 | 示例

页面导航

摘要
著录项
相似文献
相关主题

摘要

This paper deals with the problem of sizing power and ground nets in integrated circuits composed of modules, where the nets are routed in the channels between the modules. Constraints are assumed on allowable voltage drops between the chip's power and ground pads and the module's power and ground pins. Maximum current drain into each module is also assumed to be known. A procedure for determining the width of each branch in the power and ground trees is presented, where the objective is to minimize the area of the power and ground nets subject to several constraints, such as IR voltage drop and metal migration.

机译：本文讨论了在由模块组成的集成电路中确定电源和接地网的大小的问题，其中这些网在模块之间的通道中布线。假设约束条件是芯片的电源和接地垫与模块的电源和接地引脚之间的允许压降。还假定每个模块的最大电流消耗是已知的。提出了一种确定电源树和接地树中每个分支的宽度的过程，其目的是在受到多个约束（例如IR压降和金属迁移）的情况下，最大程度地减小电源和接地网的面积。

著录项

来源
《Wireless Technology》|1996年|p.794-797|共4页
会议地点
作者
Chowdhury S.; Breuer M.A.;
展开▼
作者单位

Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA;

展开▼
会议组织
原文格式 PDF
正文语种 eng
中图分类自动化技术、计算机技术;
关键词

相似文献

外文文献
中文文献
专利

1. Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution [J] . Kriplani H., Najm F.N. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 1995,第8期

机译：CMOS VLSI电路的电源和接地总线中与模式无关的最大电流估计：算法，信号相关性及其分辨率
2. An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference [J] . Sawada Takuya, Yoshikawa Kumpei, Takata Hidehiro, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2015,第10期

机译：扩展的直接功率注入方法用于VLSI电路就地抗电磁干扰特性
3. An Efficient Multi-Objective Genetic Algorithm for Low Power Testing of Crosstalk Delay Faults in VLSI Circuits [J] . S. Jayanthy, M.C. Bhuvaneswari Advances in modelling and analysis . 2011,第1a2期

机译：低功耗测试VLSI电路中串扰延迟故障的高效多目标遗传算法
4. The construction of minimal area power and ground nets for VLSI circuits [C] . S. Chowdhury, M. A. Breuer ACM/IEEE conference on Design automation . 1985

机译：VLSI电路的最小面积电源和接地网的构建
5. Analysis and design of power and ground networks for VLSI circuits. [D] . Kozhaya, Joseph Nicolas. 2001

机译：VLSI电路的电源和接地网络的分析和设计。
6. Wirelessly powered fully internal optogenetics for brain spinal and peripheral circuits in mice [O] . Kate L Montgomery, Alexander J Yeh, John S Ho, -1

机译：无线供电的全内部光遗传学技术可用于小鼠的大脑脊髓和外围电路
7. Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution [O] . Harish Kriplani, Farid Najm, Ibrahim Hajj 1995

机译：CmOs VLsI电路的电源和接地总线中的模式独立最大电流估计：算法，信号相关性及其分辨率

The Construction of Minimal Area Power and Ground Nets for VLSI Circuits

摘要

著录项

相似文献

相关主题

期刊订阅