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首页> 外文学位 >System oriented delta sigma analog-to-digital modulator design for ultra high precision data acquisition applications.
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System oriented delta sigma analog-to-digital modulator design for ultra high precision data acquisition applications.

机译：面向系统的delta sigma模数调制器设计，用于超高精度数据采集应用。

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摘要

The demand for high-performance and power scalable DSP processors for telecommunication and portable devices has increased significantly in recent years. The Fast Fourier Transform (FFT) computation is essential to such designs. This work presents a switch-based architecture to design radix-2 FFT processors. The processor employs M processing elements, 2M memory arrays and M Read Only Memories (ROMs). One processing element performs one radix-2 butterfly operation. The memory arrays are designed as single-port memory, where each has a size of N/(2M); N is the number of FFT points. Compared with a single processing element, this approach provides a speedup of M. If not addressed, memory collisions degrade the processor performance. A novel algorithm to detect and resolve the collisions is presented. When a collision is detected, a memory management operation is executed. The performance of the switch architecture can be further enhanced by pipelining the design, where each pipeline stage employs a switch component. The result is a speedup of Mlog 2N compared with a single processing element performance.;The utilization of single-port memory reduces the design complexities and area. Furthermore, memory arrays significantly reduce power compared with the delay elements used in some FFT processors. The switch-based architecture facilitates deactivating processing elements for power scalability. It also facilitates implementing different FFT sizes.;The VLSI implementation of a non-pipeline switch-based processor is presented. Matlab simulations are conducted to analyze the performance. The timing, power and area results from RTL, synthesis and layout simulations are discussed and compared with other processors.
机译：近年来，电信和便携式设备对高性能和可扩展功率的DSP处理器的需求已大大增加。快速傅立叶变换（FFT）计算对于此类设计至关重要。这项工作提出了一种基于开关的体系结构来设计基数为2的FFT处理器。该处理器采用M个处理元件，2M个存储阵列和M个只读存储器（ROM）。一个处理元件执行一个基数为2的蝶形运算。内存阵列设计为单端口内存，每个内存阵列的大小为N /（2M）。 N是FFT点数。与单个处理元素相比，此方法可提供M的加速。如果不解决，内存冲突将降低处理器性能。提出了一种检测和解决碰撞的新颖算法。当检测到冲突时，执行存储器管理操作。可以通过对设计进行流水线化来进一步提高交换架构的性能，其中每个流水线级都使用一个交换组件。结果是与单个处理元件性能相比，Mlog 2N的速度得到了提高。；单端口内存的利用降低了设计的复杂性和面积。此外，与某些FFT处理器中使用的延迟元件相比，存储器阵列显着降低了功耗。基于开关的体系结构有助于停用处理元素以实现电源可伸缩性。它还有利于实现不同的FFT大小。提出了一种基于非流水线开关的处理器的VLSI实现。进行Matlab仿真以分析性能。讨论了RTL，综合和布局仿真产生的时序，功率和面积结果，并与其他处理器进行了比较。

著录项

  • 作者

    Yang, YuQing.;

  • 作者单位

    The University of Texas at Austin.;

  • 授予单位 The University of Texas at Austin.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2008
  • 页码 172 p.
  • 总页数 172
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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