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High speed circuit techniques for network intrusion detection systems (NIDS).

机译:用于网络入侵检测系统(NIDS)的高速电路技术。

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摘要

This thesis presents a string matching hardware implemented on FPGA platforms for network intrusion detection systems. The proposed architecture, consisting of packet classifiers and strings matching verifiers, achieves superb throughput by using several mechanisms. First, based on incoming packet contents, the packet classifier scan dramatically reduce the number of strings to be matched for each packet and, accordingly, feed the packet to a proper verifier to conduct matching. Second, a novel multi-threading finite state machine (FSM) is proposed, which improves FSM clock frequency and allows multiple packets to be examined by a single FSM simultaneously. Design techniques for high-speed interconnect and interface circuits are also presented. Experimental results are presented to explore the trade-offs between system performance, strings partition granularity and hardware resource cost.
机译:本文提出了一种在FPGA平台上实现的用于网络入侵检测系统的字符串匹配硬件。所提出的体系结构由数据包分类器和字符串匹配检验器组成,它通过使用多种机制实现了卓越的吞吐量。首先,基于传入的数据包内容,数据包分类器扫描将大大减少每个数据包要匹配的字符串数,并相应地将数据包馈送到适当的验证程序以进行匹配。其次,提出了一种新颖的多线程有限状态机(FSM),它提高了FSM时钟频率,并允许单个FSM同时检查多个数据包。还介绍了用于高速互连和接口电路的设计技术。给出实验结果以探索系统性能,字符串分区粒度和硬件资源成本之间的折衷。

著录项

  • 作者

    Mahajan, Atul.;

  • 作者单位

    Southern Illinois University at Carbondale.;

  • 授予单位 Southern Illinois University at Carbondale.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 M.S.
  • 年度 2008
  • 页码 58 p.
  • 总页数 58
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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