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Efficient VLSI divide and conquer array architectures for multiplication.

机译：高效的VLSI分治阵列结构，以实现乘法。

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摘要

In this dissertation, we introduce an efficient VLSI array architecture for binary multiplication, and discuss its extension for vector-scalar multiplication. The architectures are based on an existing parameterized divide and conquer algorithm that uses optimal partitioning and redundancy removal for simultaneous computation of partial sums.; Four versions of the proposed Parameterized Binary Multiplier Architecture (PBMA), two for the general case where the multiplicand and the multiplier are variables (PBMA-A and PBMA-AT) and two for the special case where the multiplier is programmable constant (cPBMA-A and cPBMA-AT), are implemented and compared to the conventional Carry-Save Array Multiplier implementation. PBMA-A is optimized for area (A) and is shown to achieve significant area (A) savings at the cost of increased operational delay (T), while PBMA-AT is optimized for area-time product (AT) and is shown to achieve significant area-time product (AT) savings and a smaller operational delay (T) at the cost of smaller area (A) savings. cPBMA-A is optimized for area (A) and is shown to achieve significant area (A) savings without any major impact on operational delay (T), while cPBMA-AT is optimized for area-time product (AT) and is shown to achieve significant area-time product (AT) savings and a significantly smaller operational delay (T) at the cost of slightly smaller area (A) savings. All versions are also shown to be highly power (P) efficient.; Four versions of the proposed Parameterized Vector-Scalar Multiplier Architecture (PVSMA), two for the general case where the vector and the scalar are variables (PVSMA-A and PVSMA-AT) and two for the special case where the scalar is programmable constant (cPVSMA-A and cPVSMA-AT), are implemented and compared to the conventional parallel implementation with Carry-Save Array Multipliers. PVSMA-A is optimized for area (A) and is shown to achieve significant area (A) savings at the cost of increased operational delay (T), while PVSMA-AT is optimized for area-time product (AT) and is shown to achieve significant area-time product (AT) savings and a smaller operational delay (T) at the cost of smaller area (A) savings. cPVSMA-A is optimized for area (A) and is shown to achieve significant area (A) savings without any major impact on operational delay (T), while cPVSMA-AT is optimized for area-time product (AT) and is shown to achieve significant area-time product (AT) savings and a significantly smaller operational delay (T) at the cost of slightly smaller area (A) savings. All versions are also shown to be highly power (P) efficient.
机译：本文介绍了一种高效的二进制乘法VLSI阵列架构，并讨论了其对矢量标量乘法的扩展。这些架构基于现有的参数化分而治之算法，该算法使用最佳划分和冗余去除来同时计算部分和。拟议的参数化二进制乘法器体系结构（PBMA）的四个版本，两个用于被乘数和乘数是变量的一般情况（PBMA-A和PBMA-AT），两个用于乘数是可编程常数的特殊情况（cPBMA- A和cPBMA-AT）已实现，并与传统的“进位保存阵列乘法器”实现进行了比较。 PBMA-A针对区域（A）进行了优化，并显示出可节省大量区域（A），但以增加的操作延迟（T）为代价，而PBMA-AT针对区域时间乘积（AT）进行了优化，并显示出以节省面积（A）为代价，实现了显着的时空积（AT）节省和较小的操作延迟（T）。 cPBMA-A针对区域（A）进行了优化，并显示出可实现显着的区域（A）节省，而对操作延迟（T）没有任何重大影响，而cPBMA-AT针对区域时积（AT）进行了优化。以节省的面积（A）略微为代价，实现了节省大量的时域积（AT）并显着降低了运行延迟（T）。所有版本还显示出高功率（P）效率。拟议的参数化矢量-标量乘法器体系结构（PVSMA）的四个版本，两个用于矢量和标量为变量的常规情况（PVSMA-A和PVSMA-AT），两个用于标量为可编程常数的特殊情况（实施了cPVSMA-A和cPVSMA-AT，并与带有进位保存阵列乘法器的常规并行实施进行了比较。 PVSMA-A针对区域（A）进行了优化，并显示出可节省大量区域（A），但以增加的操作延迟（T）为代价，而PVSMA-AT针对区域时间乘积（AT）进行了优化，并显示出以节省面积（A）为代价，实现了显着的时空积（AT）节省和较小的操作延迟（T）。 cPVSMA-A针对区域（A）进行了优化，并显示出可节省大量区域（A），而对操作延迟（T）没有任何重大影响，而cPVSMA-AT针对区域时间乘积（AT）进行了优化。以节省的面积（A）略微为代价，实现了节省大量的时域积（AT）并显着降低了运行延迟（T）。所有版本还显示出高功率（P）效率。

著录项

  • 作者

    Poonnen, Thomas.;

  • 作者单位

    State University of New York at Buffalo.$bElectrical Engineering.;

  • 授予单位 State University of New York at Buffalo.$bElectrical Engineering.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2007
  • 页码 155 p.
  • 总页数 155
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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