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Current and delay estimation in deep sub-micrometer CMOS logic circuits.

机译：深亚微米CMOS逻辑电路中的电流和延迟估计。

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摘要

The continual shrinking of CMOS device features raises some problems; one of the most relevant is signal propagation delay estimation. Using the circuit simulator is prohibitively time consuming. Faster, yet, accurate delay estimation methods are strongly needed. The propagation delay is affected by MOSFET current and capacitance, the applied signal slope and the number of serially connected MOSFETs.; This work proposes an extended MOSFET saturation current model for deep submicrometer technologies by adding the channel-length modulation effects. Moreover, the thesis proposes four classes of MOSFET capacitance models. These classes differ in the number of parameters they use to characterize MOSFET capacitances. In addition, the work adopts one more MOSFET capacitance class from the literature that recognizes the difference between the capacitances associated with a rising transition and those associated with falling transition.; Furthermore, the dissertation proposes four delay model levels that are related to the MOSFET capacitance classes. Also, two more delay levels are adopted from the literature: one that is based on logical effort technique and a more complicated one that is based on Shams model. Shams model is modified to give two more delay model levels. One of them uses a simpler way of accounting for the effect of serially-connected MOSFETs. The other one uses a more complicated expression for the input slope effect. An empirical technique to estimate the linear and quadratic effects of the input signal slope on the delay is also proposed.; The study is performed on 0.13 mum and 90 nm CMOS technologies to demonstrate how much complexity and details are required for reasonably accurate delay estimation.
机译：CMOS器件功能的不断缩小带来了一些问题。最相关的一种是信号传播延迟估计。使用电路仿真器非常耗时。迫切需要更快，更准确的延迟估计方法。传播延迟受MOSFET电流和电容，施加的信号斜率以及串联连接的MOSFET数量的影响。这项工作通过增加沟道长度调制效应，为深亚微米技术提出了扩展的MOSFET饱和电流模型。此外，本文提出了四类MOSFET电容模型。这些类别在用于表征MOSFET电容的参数数量上有所不同。此外，这项工作还采用了文献中的另一种MOSFET电容类别，该类别可识别与上升过渡相关的电容与与下降过渡相关的电容之间的差异。此外，本文提出了与MOSFET电容等级有关的四个延迟模型水平。此外，文献中还采用了另外两种延迟级别：一种基于逻辑努力技术，另一种基于Shams模型。修改了Shams模型，以提供两个以上的延迟模型级别。其中之一采用了一种更简单的方法来解决串联MOSFET的影响。另一个使用更复杂的表达式来表示输入斜率效果。还提出了一种估算输入信号斜率对延迟的线性和二次影响的经验技术。这项研究是在0.13微米和90纳米CMOS技术上进行的，旨在证明合理准确的延迟估计需要多少复杂性和细节。

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  • 作者

    Al-Mosawy, Muaayad.;

  • 作者单位

    Carleton University (Canada).;

  • 授予单位 Carleton University (Canada).;
  • 学科 Engineering Electronics and Electrical.
  • 学位 M.A.Sc.
  • 年度 2007
  • 页码 124 p.
  • 总页数 124
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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