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VLSI architectures for LDPC encoder/decoder in WiMAX.

机译：WiMAX中用于LDPC编码器/解码器的VLSI体系结构。

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One of the main goals of any communication system is to transfer data reliably from source to destination. In particular, wireless communication medium is very noisy, so new techniques are to be used for error-control to ensure robust data transmission. Channel coding is the most popular and widely used error-control technique that makes use of channel codes. Shannon, considered the father of modern information theory, showed that every channel has certain threshold data-rate called the capacity below which reliable transmission is possible and above which transmission will result in un-recoverable errors. Thus, the goal of every channel code is to come as close to this limit as possible and still be practical to implement.; Turbo codes introduced in 1993 and Low-Density Parity-Check (LDPC) codes first introduced in 1963 are among such powerful channel codes. These LDPC codes were forgotten for 30 years because of their implementation complexity and lack of advancements in VLSI technology, until their rediscovery in the early 90's. Fortunately, recent advancements in VLSI technology have made it possible to implement LDPC decoding algorithms. Additionally, LDPC decoding algorithms can be highly parallelized and implemented more efficiently. Because of the above key advantages, LDPC has been adopted in all the emerging wireless standards. With the advent of these new wireless standards, the envelope of data rate is being pushed even higher. These requirements translate into high speed implementation of various channel coding schemes and at the same time these designs should occupy lower area and power.; The serial architectures for LDPC encoder/decoder available in literature are not capable of achieving high throughputs and other parallel structures do not provide a generic and a scalable architecture to support multiple standards. This Master's thesis implements a high throughput VLSI architecture for LDPC encoder as well as decoder. The proposed structure is also generic and scalable, supporting multiple standards. A generic scalable min unit is presented, which performs min-sum decoding, an approximation of the original belief propagation algorithm used in the decoding of LDPC codes. The proposed LDPC decoder is implemented as a parallel structure with high degree of pipelining. It supports any regular/irregular LDPC codes from any standard that define parity check matrix as a combination of identity matrix, shifted identity matrix and all-zero matrix. This architecture was synthesized using standard TSMC 0.18mum process technology with supply voltage of 1.8V. The achieved gate count of the proposed LDPC encoder and decoder was 71K and 810K (with full pipelined datapath), respectively.
机译：任何通信系统的主要目标之一就是将数据从源可靠地传输到目的地。特别地，无线通信介质非常嘈杂，因此将使用新技术进行差错控制以确保可靠的数据传输。信道编码是利用信道代码的最流行和广泛使用的差错控制技术。香农，被认为是现代信息理论之父，表明每个信道都有一定的阈值数据速率，称为容量，在该容量以下，可靠的传输是可能的，在该容量之上的传输将导致不可恢复的错误。因此，每个通道代码的目标是尽可能接近此限制，并且仍然很实用。这样强大的信道代码包括1993年推出的Turbo码和1963年首次引入的低密度奇偶校验（LDPC）码。这些LDPC代码由于实现复杂性和VLSI技术的缺乏而被遗忘了30年，直到90年代初重新发现为止。幸运的是，VLSI技术的最新发展使得实现LDPC解码算法成为可能。另外，LDPC解码算法可以高度并行化，并且可以更有效地实现。由于上述关键优势，LDPC已被所有新兴的无线标准所采用。随着这些新的无线标准的出现，数据速率的范围进一步提高。这些要求转化为各种信道编码方案的高速实现，同时这些设计应占用较小的面积和功耗。文献中提供的LDPC编码器/解码器的串行体系结构无法实现高吞吐量，而其他并行结构则无法提供通用且可扩展的体系结构来支持多种标准。本硕士论文为LDPC编码器和解码器实现了高吞吐量VLSI架构。提议的结构也是通用且可扩展的，支持多种标准。提出了一个通用的可伸缩最小单位，该单位执行最小和解码，这是在LDPC码解码中使用的原始置信传播算法的近似值。所提出的LDPC解码器被实现为具有高度流水线化的并行结构。它支持来自任何标准的任何常规/不规则LDPC码，这些标准将奇偶校验矩阵定义为身份矩阵，移位的身份矩阵和全零矩阵的组合。该架构是使用标准TSMC0.18μm工艺技术合成的，电源电压为1.8V。所提出的LDPC编码器和解码器的门数分别为71K和810K（具有完整的流水线数据路径）。

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