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A programmable frequency divider having a wide division ratio range, and close-to-50% output duty-cycle.

机译：具有宽分频比范围和接近50％输出占空比的可编程分频器。

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摘要

In Radio Frequency (RF) integrated circuit design field, programmable dividers are getting more and more attentions in recent years. A programmable frequency divider can divide an input frequency by programmable ratios [1]. It is a key component of a frequency synthesizer. It also can be used to generate variable clock-signals for: switched-capacitor filters (SCFs), digital systems with different power-states, as well as multiple clock-signals on the same system-on-a-chip (SOC). These circuits need high performance programmable frequency dividers, operating at high frequencies and having wide division ratio ranges, with binary division ratio controls and 50% output duty-cycle.; Different types of programmable frequency dividers are reviewed and compared. A programmable frequency divider with a wide division ratio range of (8 ∼ 524287) has been reported [2]. Because the output duty-cycle of this reported divider is far from 50%, the circuit in [2] has very limited applications. The proposed design solves this problem, without compromising other advantages of the design in [2]. The proposed design is fabricated in a 0.18-mum RF CMOS process. Test results show that the output duty-cycle is 50% when the division ratio is an even number. The duty-cycle is 44.4% when the division ratio is 9. The output duty-cycle becomes closer to 50% when the division ratio is an increasing odd number. For each division ratio, the output duty-cycle remains constant, with different input frequencies from GHz down to kHz ranges, with different temperatures and power supply voltages. This thesis provides an explanation of the design details and test results.; A Phase Locked-Loop (PLL) based frequency synthesizer can generate different output frequencies. A programmable frequency divider is an important component of this type of PLL. Since bandwidth is expensive, it is preferred to reduce the frequency channel distance of a frequency synthesizer. Using a fractional programmable divider, the frequency channel distance of a PLL can be reduced, without reducing the reference frequency or increasing the settling time of the PLL. A frequency synthesizer with a programmable fractional divider is designed and fabricated. A brief description of the PLL design and test results are presented in this dissertation.
机译：在射频（RF）集成电路设计领域，可编程分频器近年来受到越来越多的关注。可编程分频器可将输入频率除以可编程比率[1]。它是频率合成器的关键组件。它还可用于生成可变时钟信号，用于：开关电容器滤波器（SCF），具有不同电源状态的数字系统，以及同一片上系统（SOC）上的多个时钟信号。这些电路需要高性能的可编程分频器，在高频​​率下工作并且具有宽的分频比范围，并具有二进制分频比控制和50％的输出占空比。审查并比较了不同类型的可编程分频器。据报道，可编程分频器的分频比范围为（8〜524287）[2]。由于该报告的分频器的输出占空比远非50％，因此[2]中的电路应用非常有限。提出的设计解决了这个问题，而没有损害[2]中设计的其他优点。拟议的设计采用0.18微米的RF CMOS工艺制造。测试结果表明，当分频比为偶数时，输出占空比为50％。当分频比为9时，占空比为44.4％。当分频比为奇数递增时，输出占空比接近50％。对于每个分频比，在从GHz到kHz范围内的不同输入频率，不同的温度和电源电压下，输出占空比保持恒定。本文对设计细节和测试结果进行了解释。基于锁相环（PLL）的频率合成器可以生成不同的输出频率。可编程分频器是此类PLL的重要组成部分。由于带宽昂贵，因此优选减小频率合成器的频道距离。使用分数可编程分频器，可以减小PLL的频道距离，而无需降低参考频率或增加PLL的建立时间。设计并制造了带有可编程分数分频器的频率合成器。本文简要介绍了PLL设计和测试结果。

著录项

  • 作者

    Zhang, Mo.;

  • 作者单位

    The University of Tennessee.;

  • 授予单位 The University of Tennessee.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2007
  • 页码 122 p.
  • 总页数 122
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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