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Development and implementation of interactive three-dimensional video environment on Run-Time Reconfigurable FPGA platform.

机译：在运行时可重配置FPGA平台上开发和实现交互式三维视频环境。

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摘要

Video data processing tasks are traditionally performed either through software-based systems when various algorithms must be applied to the data and when time issue is not critical, DSPs---when certain time constraints are set but when the set of tasks is limited, or ASICs---when the highest performance is required, the set of tasks is fixed and highly optimized, the data stream doesn't change, and the number of data streams is limited.;The thesis presents a real-time stereo vision system with elements of synthesis of interactive 3-D virtual objects designed and implemented on the FPGA-based reconfigurable platform. FPGA chip integrates a hybrid architecture system with multi-mode and multi-stream processing ability for time critical tasks and with embedded microprocessor(s) for computing complex algorithms for 3-D objects synthesis for which timing requirements are not so strict.;An approach for the formal presentation and processing of the 3-D virtual objects and their transformation is also analyzed and presented in this paper. Architecture synthesis and optimization for a hybrid system are also considered.;The experimental results proved the effectiveness of proposed approach: the FPGA-based system-on-chip provides stereo visualization in different modes (actual image and edge detection image), with synthesized 3-D controls (pressed and released buttons).;For a real-time system which must operate on multiple data streams which also can change in time and on which various data processing algorithms must be applied neither of the mentioned approaches can be used. Timing requirements and power limitation does not allow utilization of a sequential CPU. ASIC becomes too big to accommodate multiple processing circuits for each algorithm and associated modes. Only Run-Time Reconfigurable (RTR) FPGA approach allows implementation of such a system.;Keywords. Stereo Vision, 3-D Synthesis, Reconfigurable Platform, FPGA
机译：传统上，视频数据处理任务是通过基于软件的系统执行的，这时必须将各种算法应用于数据，而对于时间问题不是很关键的情况，则是在设置了特定时间限制但任务集受到限制的情况下，DSP；或者ASIC-当需要最高性能时，固定的任务集和高度优化的数据流不会发生变化，并且数据流的数量会受到限制。在基于FPGA的可重配置平台上设计和实现的交互式3-D虚拟对象的综合元素。 FPGA芯片将混合架构系统与具有多模式和多流处理能力的关键任务集成在一起，并与嵌入式微处理器集成在一起，用于计算复杂的算法以进行3D对象合成，而这些对象对时序的要求并不严格。本文还对3-D虚拟对象的形式表示和处理以及它们的转换进行了分析和介绍。实验结果证明了该方法的有效性：基于FPGA的片上系统提供了不同模式下的立体可视化效果（实际图像和边缘检测图像），其中合成3 -D控件（按下和释放按钮）。对于必须在多个数据流上运行的实时系统，该数据流也可以随时间变化，并且必须在其上应用各种数据处理算法，但不能使用上述方法。时序要求和功率限制不允许使用顺序CPU。 ASIC太大了，无法为每种算法和相关模式容纳多个处理电路。只有运行时可重配置（RTR）FPGA方法才允许实现这样的系统。立体视觉，3D综合，可重构平台，FPGA

著录项

  • 作者

    Zhelnakov, Sergiy.;

  • 作者单位

    Ryerson University (Canada).;

  • 授予单位 Ryerson University (Canada).;
  • 学科 Engineering Electronics and Electrical.
  • 学位 M.A.Sc.
  • 年度 2006
  • 页码 121 p.
  • 总页数 121
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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