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An analytical and numerical model for design of non-uniformly powered silicon chips based on both thermal and device clock performance.

机译：基于热和器件时钟性能的非均匀供电硅芯片设计的解析和数值模型。

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摘要

Silicon chips continue to grow in capabilities, complexity and performance. Silicon chips typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the chip. However, the integration also introduces a layer of complexity in the thermal design and management of silicon chips. As a direct result of functional integration, the power map on a silicon chip is typically highly non-uniform and the assumption of a uniform heat flux across the chip surface has been shown to be invalid post Pentium II architecture.; The active side of the silicon chip is divided into several functional blocks with distinct power assigned to each functional block. Current research is focusing on microprocessor as a leading example but the work applies equally to other applications where silicon chips demonstrate non-uniformity. For instance graphic chips can exhibit non-uniformity so can ASICs.; Initially, a numerical model is developed to minimize the on-die temperature of the package by optimizing the distribution of the non-uniformly powered functional blocks with different power matrices. In order to model the non-uniformly power dissipation on the silicon chip, the chip surface area is divided into different cases such as 3 x 3, 4 x 4, 8 x 8, 10 x 10 etc. of power matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other is carried out in order to minimize the junction temperature Tj (Maximum temperature on die). The best possible Tjmax reduction could thus be found. Based on the data derived from numerical model, for different power matrices, trend for the data is evaluated which helps to draw design guideline for a typical die configuration (i.e. 30 x 30).; This is followed with a development of an analytical approach to temperature distribution of a first level package with a non-uniformly powered die which is carried for the first time. Previously developed analytical model [18] for two layer bodies is extended to this typical package which is a multilayer body. The solution is to begin by designating each surface heat flux as a volumetric heat source. An inverse methodology is applied to solve the equations for various surfaces to calculate maximum junction temperature for given multilayer body. Finally validation of the analytical solution is carried out using developed numerical model.; In the end, a multi-objective optimization is carried out embedding developed numerical model into silicon floor plan to developed compact model satisfying both electrical and thermal performance. Recommendations are provided for an architecture design regarding maximum separation of functional block with minimum on-die temperature. The commercial finite element code ANSYSRTM is used in this study.
机译：硅芯片在功能，复杂性和性能方面不断增长。硅芯片通常在其体系结构中集成功能组件，例如逻辑和二级（L2）缓存。逻辑和存储器的这种功能集成可提高芯片的性能。但是，集成还为硅芯片的热设计和管理带来了一层复杂性。功能集成的直接结果是，硅芯片上的功率图通常高度不均匀，并且在奔腾II架构之后，对整个芯片表面均匀热通量的假设已被证明是无效的。硅芯片的有源侧分为几个功能块，每个功能块分配有不同的功率。当前的研究集中在微处理器作为一个领先的例子，但是这项工作同样适用于硅芯片显示出不均匀性的其他应用。例如，图形芯片可能表现出非均匀性，而ASIC也可能表现出非均匀性。最初，通过优化具有不同功率矩阵的非均匀供电功能块的分布，开发了一个数值模型以最小化封装的芯片上温度。为了模拟硅芯片上的非均匀功耗，将芯片表面积分为具有矩阵空间的功率矩阵的不同情况，例如3 x 3、4 x 4、8 x 8、10 x 10等。代表具有恒定热通量的独特功能块。最后，使用FEM代码对功能块之间的相对位置进行优化，以使结温Tj（芯片上的最高温度）最小。因此可以找到最佳的Tjmax降低。根据数值模型得出的数据，对于不同的功率矩阵，可以评估数据的趋势，这有助于得出典型模具配置（即30 x 30）的设计准则。这之后是一种分析方法的发展，该分析方法用于首次携带的具有不均匀供电的芯片的第一级封装的温度分布。先前针对两层体开发的分析模型[18]扩展到了这种典型的多层体包装。解决方案是通过将每个表面热通量指定为体积热源开始。应用逆方法来求解各种表面的方程，以计算给定多层体的最大结温。最后，使用开发的数值模型对分析溶液进行验证。最后，进行了多目标优化，将开发的数值模型嵌入到硅平面布置图中，从而开发了既满足电性能又满足热性能的紧凑模型。提供了有关架构设计的建议，这些建议涉及以最小的芯片上温度最大程度地分离功能块。本研究使用商业有限元代码ANSYSRTM。

著录项

  • 作者

    Kaisare, Abhijit D.;

  • 作者单位

    The University of Texas at Arlington.$bMechanical Engineering.;

  • 授予单位 The University of Texas at Arlington.$bMechanical Engineering.;
  • 学科 Engineering Electronics and Electrical.; Engineering Mechanical.
  • 学位 Ph.D.
  • 年度 2007
  • 页码 76 p.
  • 总页数 76
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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