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Empirical timing analysis of CPUs and delay fault tolerant design using partial redundancy.

机译：CPU的经验时序分析和使用部分冗余的延迟容错设计。

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摘要

The operating clock frequency is determined by the longest signal propagation delay, setup/hold time, and timing margin. These are becoming less predictable with the increasing design complexity and process miniaturization. The difficult challenge is then to ensure that a device operating at its clock frequency is error-free with quantifiable assurance. Effort at device-level engineering will not suffice for these circuits exhibiting wide process variation and heightened sensitivities to operating condition stress. Logic-level redress of this issue is a necessity and we propose a design-level remedy for this timing-uncertainty problem.; The aim of the design and analysis approaches presented in this dissertation is to provide framework, SABRE, wherein an increased operating clock frequency can be achieved. The approach is a combination of analytical modeling, experimental analysis, hardware/time-redundancy design, exception handling and recovery techniques. Our proposed design replicates only a necessary part of the original circuit to avoid high hardware overhead as in triple-modular-redundancy (TMR). The timing-critical combinational circuit is path-wise partitioned into two sections. The combinational circuits associated with long paths are laid out without any intrusion except for the fan-out connections from the first section of the circuit to a replicated second section of the combinational circuit. Thus only the second section of the circuit is replicated. The signals fanning out from the first section are latches, and thus are far shorter than the paths spanning the entire combinational circuit. The replicated circuit is timed at a subsequent clock cycle to ascertain relaxed timing paths. This insures that the likelihood of mistiming due to stressor process variation is eliminated. During the subsequent clock cycle, the outcome of the two logically identical, yet time-interleaved, circuit outputs are compared to detect faults. When a fault is detected, there try signal is triggered and the dynamic frequency-step-down takes place before a pipe flush, and retry is issued. The significant timing overhead associated with the retry is offset by the rarity of the timing violation events. Simulation results on ISCAS Benchmark circuits show that 10% of clock frequency gain is possible with 10 to 20% of hardware overhead of replicated timing-critical circuit.
机译：工作时钟频率取决于最长的信号传播延迟，建立/保持时间和时序余量。随着设计复杂度的提高和工艺的小型化，这些变得越来越难以预测。因此，困难的挑战是要以可量化的保证来确保以其时钟频率运行的设备是无错误的。对于这些电路，这些电路显示出广泛的工艺变化和对工作条件应力的敏感性，因此，在器件级工程上的努力是不够的。对此问题进行逻辑级别的补救是必要的，我们针对此时序不确定性问题提出了一种设计级别的补救措施。本文提出的设计和分析方法的目的是提供一种框架SABRE，可以提高工作时钟频率。该方法是分析建模，实验分析，硬件/时间冗余设计，异常处理和恢复技术的组合。我们提出的设计仅复制了原始电路的必要部分，以避免像三重模块冗余（TMR）那样的高硬件开销。时序关键型组合电路按路径分为两部分。与长路径相关的组合电路的布局没有任何干扰，除了从电路的第一部分到组合电路的复制的第二部分的扇出连接之外。因此，仅复制电路的第二部分。从第一部分散开的信号是锁存器，因此比跨越整个组合电路的路径短得多。在随后的时钟周期对复制电路进行计时，以确定松弛的时序路径。这确保消除了由于压力源过程变化而产生雾化的可能性。在随后的时钟周期中，将两个逻辑相同但经过时间交错的电路输出的结果进行比较，以检测故障。当检测到故障时，触发尝试信号，并在管道冲洗之前发生动态降频，然后发出重试。与重试相关的大量时序开销被时序冲突事件的稀有性所抵消。在ISCAS Benchmark电路上的仿真结果表明，时钟频率增益的10％是可能的，而复制的时序关键电路的硬件开销为10％到20％。

著录项

  • 作者

    Chang, Sanghoan.;

  • 作者单位

    Texas A&M University.;

  • 授予单位 Texas A&M University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2007
  • 页码 93 p.
  • 总页数 93
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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