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Design and realization of a single stage sigma-delta ADC with low oversampling ratio.

机译：低过采样率的单级sigma-delta ADC的设计与实现。

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摘要

Due to the rapid growth of the communication market, a large amount of research is in process toward a high speed and high resolution sigma-delta A/D converter. This dissertation focuses on the design of a single-stage sigma-delta A/D converter with very low oversampling ratio for the wireless application. An architecture for a multibit single-stage delta-sigma A/D converter with two-step quantization is proposed. Both the MSB and LSB signals produced by the two-step quantization are fed back simultaneously to all integrator stages, making it suitable for low oversampling ratios. The two-step ADC avoids the problem that the complexity of an internal flash ADC increases exponentially with each added bit. A segmented architecture with coarse/fine DEM and DAC is proposed to reduce the complexity of DEM and DAC due to the large internal quantizer. The consequence of the segmentation, mismatch between coarse and fine DACs can be noise-shaped by using a digital requantization (REQ) algorithm. A second-order single-stage sigma-delta A/D converter with 8-bit two-step inner quantization is proposed in this dissertation, which employs the feed-forward branches to reduce the integrator output swing. The proposed modulator is implemented with TSMC 0.25 mum mixed-signal process, using the switched-capacitor circuit. The measured system achieves the dynamic range of 70 dB under an oversampling ratio of 16 with the REQ algorithm reducing the noise floor in the signal bandwidth by 20 dB.
机译：由于通信市场的快速增长，正在对高速和高分辨率sigma-delta A / D转换器进行大量研究。本文针对无线应用中过采样率极低的单级sigma-delta A / D转换器的设计进行了研究。提出了一种具有两步量化的多位单级delta-sigma A / D转换器的体系结构。由两步量化产生的MSB和LSB信号同时反馈到所有积分器级，使其适用于低过采样率。两步ADC避免了内部闪存ADC的复杂度随每个增加的位呈指数增长的问题。提出了一种具有粗/细DEM和DAC的分段架构，以降低由于内部量化器较大而导致的DEM和DAC的复杂性。通过使用数字重新量化（REQ）算法，可以对噪声，粗略DAC与精细DAC之间的不匹配进行分段以消除噪声。本文提出了一种具有8位两步内部量化的二阶单级sigma-delta A / D转换器，该转换器采用前馈分支来减小积分器的输出摆幅。所提出的调制器是使用TSMC0.25μm混合信号工艺，使用开关电容电路来实现的。使用REQ算法，被测系统在16的过采样比下可实现70 dB的动态范围，从而将信号带宽的本底噪声降低了20 dB。

著录项

  • 作者

    Cheng, Yongjie.;

  • 作者单位

    Brigham Young University.;

  • 授予单位 Brigham Young University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2006
  • 页码 138 p.
  • 总页数 138
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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