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Memory interface architecture for network on chip based systems.

机译：用于基于芯片的系统的内存接口体系结构。

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摘要

Advances in VLSI has made it possible to integrate heterogeneous modules on the same chip leading to System On Chip based designs. Network-on-Chip (NoC) has been suggested as the communication resource to overcome the on-chip physical interconnect issues for complex System-on-Chips (SoCs). Present and future NoC based SoCs are designed using preexisting components such as CPUs, DSPs, memories, which we call Cores. The SoC concept facilitates the reuse of IP cores in a plug and play manner. This research proposes a novel architecture in which most of the interfacing functionality is incorporated in the generic part of the interface.; Several applications types (networking, computer graphics and multimedia applications) require a large memory space. Memory issues play an important role in the design of application-specific systems. In an SoC, there arises the problem of providing a large memory space to provide memory to all cores interface on the SoC. This thesis provides a novel Memory Organization and Packing style to ensure that the Memory Core that is interfaced on an NoC based SoC is used to its maximum capacity, without any wastage of Memory space.; For different applications e.g. Video, Communication, Computing etc., IP Cores will have different memory requirements in the same SoC design. SoC designs give the flexibility to interface an IP Core with a non-standard data width size. An architectural interface between a Memory Core and the underlying network interface to abstract varying data width sizes of different IP Cores is also presented here. In this way, IP Cores of varying aspect ratio and memory requirements, can use a single Memory Core on the SoC.
机译：VLSI的进步使得将异构模块集成在同一芯片上成为可能，从而实现了基于系统芯片的设计。片上网络（NoC）已被建议作为通信资源来克服复杂的片上系统（SoC）的片上物理互连问题。当前和将来的基于NoC的SoC是使用CPU，DSP，存储器等预先存在的组件（我们称为内核）来设计的。 SoC概念以即插即用的方式促进了IP核的重用。这项研究提出了一种新颖的架构，其中大多数接口功能都包含在接口的通用部分中。几种应用程序类型（网络，计算机图形和多媒体应用程序）需要很大的存储空间。内存问题在专用系统的设计中起着重要作用。在SoC中，出现了提供大的存储器空间以向SoC上的所有内核接口提供存储器的问题。本文提供了一种新颖的内存组织和打包方式，以确保在基于NoC的SoC上连接的内存内核被使用到其最大容量，而不会浪费任何内存空间。对于不同的应用在同一SoC设计中，视频，通信，计算等IP内核将具有不同的内存要求。 SoC设计提供了灵活的接口以非标准数据宽度大小连接IP核。此处还介绍了内存核心和基础网络接口之间的架构接口，用于抽象不同IP核心的不同数据宽度大小。这样，具有不同长宽比和内存要求的IP内核可以在SoC上使用单个内存内核。

著录项

  • 作者

    Nagda, Tanvi.;

  • 作者单位

    The University of Texas at Dallas.;

  • 授予单位 The University of Texas at Dallas.;
  • 学科 Computer Science.
  • 学位 M.S.
  • 年度 2006
  • 页码 74 p.
  • 总页数 74
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 自动化技术、计算机技术;
  • 关键词

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