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Architectural and compiler techniques for microprocessor power and performance management.

机译：用于微处理器电源和性能管理的体系结构和编译器技术。

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摘要

As computing technology continues to progress very rapidly, many technical challenges emerge. One of these is the issue of power dissipation. Indeed, power delivery and dissipation are becoming primary limiters of performance and integration for microprocessors. In response, architectural and software level power-reduction techniques, which extend traditional circuit-level energy techniques, have gained more and more attention and become an active research area in the last few years.; The work in this thesis focuses on one important problem in this area, namely dynamic power and performance management in high-performance processors. Dynamic adaptive techniques are appealing because they offer the ability to adjust on the fly according to the current run-time power and performance situation. This thesis investigates architectural and compiler techniques for controlling power and performance in microprocessors. The overall contributions of this work are the proposed new concepts, methods, and framework for intelligent power and performance management.; Specifically, this work has had two major thrusts. First, formal control-theoretic techniques will be discussed in the context of hardware-based energy control. The environment is a multiple clock domain processor. An analytical system model is first proposed that describes relationships among performance demand, capability, and clock frequency. A controller is then designed to balance the speeds of different clock islands. Experimental results show that the proposed technique is 2--3 times more efficient in terms of energy delay product improvement, compared to a previous heuristic approach. In addition, the new technique is more robust with a guaranteed stability margin even under extreme cases. For the above design, both fixed-interval and adaptive interval control schemes have been investigated. Second, software-layer energy control opportunities are explored in a general dynamic compilation system. It is shown that a dynamic compiler driven scheme has several unique features and advantages over existing energy control schemes. Such a scheme is then designed, implemented, and deployed on real hardware (with a Pentium-M processor). Experimental results from physical power measurements show up to 70% energy saving is accomplished for SPEC benchmarks. In addition, because of its orthogonal features and advantages, the dynamic compiler driven scheme can be an effective complement to existing hardware-based energy control schemes.
机译：随着计算技术的持续快速发展，出现了许多技术挑战。其中之一是功耗问题。实际上，功率的传递和功耗正成为微处理器性能和集成的主要限制因素。相应地，扩展了传统电路级能源技术的体系结构和软件级节能技术越来越受到关注，并成为近几年的活跃研究领域。本文的工作集中在这一领域的一个重要问题，即高性能处理器中的动态功耗和性能管理。动态自适应技术之所以吸引人，是因为它们提供了根据当前运行时功率和性能情况动态调整的能力。本文研究了用于控制微处理器的电源和性能的体系结构和编译器技术。这项工作的总体贡献是提出了用于智能电源和性能管理的新概念，新方法和新框架。具体来说，这项工作有两个主要重点。首先，将在基于硬件的能量控制的背景下讨论形式控制理论技术。该环境是一个多时钟域处理器。首先提出了一个分析系统模型，该模型描述了性能需求，功能和时钟频率之间的关系。然后设计一个控制器来平衡不同时钟岛的速度。实验结果表明，与以前的启发式方法相比，该技术在能量延迟产品改进方面的效率提高了2--3倍。此外，即使在极端情况下，新技术也更加强大，并具有保证的稳定性余量。对于上述设计，已经研究了固定间隔和自适应间隔控制方案。其次，在通用动态编译系统中探索软件层能量控制机会。结果表明，与现有的能量控制方案相比，动态编译器驱动的方案具有几个独特的功能和优点。然后，可以在真实的硬件上（使用Pentium-M处理器）设计，实施和部署这种方案。物理功率测量的实验结果表明，对于SPEC基准，可以节省多达70％的能源。另外，由于其正交的特性和优点，动态编译器驱动的方案可以有效地补充现有的基于硬件的能量控制方案。

著录项

  • 作者

    Wu, Qiang.;

  • 作者单位

    Princeton University.;

  • 授予单位 Princeton University.;
  • 学科 Computer Science.
  • 学位 Ph.D.
  • 年度 2006
  • 页码 123 p.
  • 总页数 123
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 自动化技术、计算机技术;
  • 关键词

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