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Novel Performance Enhancement Techniques for Delta Sigma Modulators for Telecom, Audio and Sensor Applications.

机译：用于电信，音频和传感器应用的Delta Sigma调制器的新型性能增强技术。

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摘要

The rapid growth of the market for portable, battery operated systems for communications, computer and consumer electronics (3C), and the trend of moving functionality to the digital domain in very large scale integration (VLSI) systems have resulted in an enormously increasing interest in analog-to-digital converter (ADC) design.;Combining both oversampling and quantization error shaping techniques, delta sigma (DeltaSigma) ADCs achieve a high degree of insensitivity to analog circuit imperfections. Nevertheless, the design of CMOS DeltaSigma ADCs involves a number of practical issues and trade-offs that must be taken into account in order to optimize their performance in terms of power consumption, silicon area, and time-to-market deployment. This thesis proposes a number of novel performance-enhancement techniques on different design levels, including algorithm, architecture and circuit level, for DeltaSigma ADCs in various application circumstances, such as telecom, audio, sensor, and so on.;First, novel techniques are proposed to mitigate I/Q mismatches in switched-capacitor quadrature bandpass Delta-Sigma modulators (DSMs) used in low-IF wireless receivers. The I/Q mismatches result in a nearby channel at the image frequency, the mirrored image of the desired signal around its center frequency (self-image) and the quantization noise to corrupt the desired signal, degrading the dynamic range of the modulator. A dynamic element matching scheme and a bilinear scheme are the proposed solution to reduce all the above-mentioned I/Q mismatch effects. Furthermore, a multiplexing scheme for the sharing of op-amps, quantizers and DACs between the I and Q channels is investigated for smaller chip area. A prototyping DSM was designed and fabricated in a 0.18 microm CMOS, measuring an image rejection ratio of 73 dB, being the best reported.;Second, a pulse-width-modulation (PWM) technique is proposed for on-chip automatic RC time constant tuning for cascaded continuous-time (CT) DSMs for audio application. The demand for high signal-to-noise-plus-distortion ratio (SNDR) and low power brings a wealth of opportunities to the CT DSMs. In CT DSMs, cascading low-order stages provides an effective way to achieve stable high-order modulation. However, compared to CT single-loop modulators, CT cascaded modulators are more sensitive to variation of RC time constant and finite dc gain of the opamps as these nonidealities affect the precise cancellation of the quantization noises between the analog and digital paths. In the CT cascaded modulator presented here, we propose to apply a PWM technique for on-chip automatic RC time constant tuning. The application of PWM in turn enables the use of the correlated double sampling (CDS) technique, which is conventionally confined to discrete-time circuits, to boost the effective dc gain. The PWM further allows the use of a finite-opamp-bandwidth compensation technique for power saving. Analysis on PWM tuning, CDS, anti-aliasing filtering, noise and jitter in the CT modulator are presented and verified with extensive simulations. Measurement results on a prototype CT cascaded 2-2 DSM in a 0.18-microm CMOS show that the proposed techniques can improve the dynamic range (DR), SNDR and spurious-free dynamic range (SFDR) of the modulator by at least 28 dB.;Third, a high-precision capacitance-to-digital converter (CDC) is proposed, which can be configured to interface with single-ended or differential capacitive sensors. In the conventional CDC, charge injection from bottom-plate switches depends on the digital output and the value of the sensing capacitor. Nonlinearity is resulted especially when the varying ranging of the sensing capacitor is wide. In this thesis, new switching and calibration schemes are proposed to reduce these charge injection. A prototyping 2nd order CDC employing the proposed techniques is fabricated in a 0.18-microm CMOS process and achieves a 53.2aFrms resolution in a 0.5ms measuring time. The proposed techniques improve the CDC's linearity from 9.3 bits to 12.3 bits in the single-ended sensing mode, and from 10.1 bits to 13.3 bits in the differential sensing mode, with a wide sensing capacitor range from 0.5 to 3.5pF. The CDC is also demonstrated with real-life pressure (single-ended) and acceleration (differential) sensors.
机译：用于通信，计算机和消费电子（3C）的便携式电池操作系统的市场的快速增长，以及在超大规模集成（VLSI）系统中将功能转移到数字域的趋势，引起了人们的极大兴趣模数转换器（ADC）设计。delta sigma（DeltaSigma）ADC结合了过采样和量化误差整形技术，对模拟电路缺陷具有高度的不敏感性。尽管如此，CMOS DeltaSigma ADC的设计仍涉及许多实际问题和折衷，以便在功耗，芯片面积和上市时间方面优化其性能。本文针对DeltaSigma ADC在电信，音频，传感器等各种应用环境下，提出了许多不同设计，性能，技术水平的新颖技术，包括算法，体系结构和电路级。提出减轻在低中频无线接收器中使用的开关电容器正交带通Delta-Sigma调制器（DSM）中的I / Q不匹配的建议。 I / Q不匹配会导致附近的某个信道处于镜像频率，其中心频率附近的所需信号的镜像图像（自身图像）和量化噪声破坏所需信号，从而降低了调制器的动态范围。提出了一种动态元素匹配方案和双线性方案来减少上述所有I / Q失配效应。此外，针对较小的芯片面积，研究了用于在I和Q通道之间共享运算放大器，量化器和DAC的复用方案。原型DSM在0.18微米CMOS上设计和制造，测量的镜像抑制比为73 dB，是最好的报告。其次，提出了一种用于片上自动RC时间常数的脉宽调制（PWM）技术。调整音频应用的级联连续时间（CT）DSM。对高信噪比失真比（SNDR）和低功耗的需求为CT DSM带来了许多机遇。在CT DSM中，级联的低阶级提供了一种实现稳定的高阶调制的有效方法。但是，与CT单回路调制器相比，CT级联调制器对RC时间常数的变化和运算放大器的有限dc增益更敏感，因为这些非理想因素会影响模拟路径和数字路径之间量化噪声的精确消除。在此处介绍的CT级联调制器中，我们建议将PWM技术应用于片上自动RC时间常数调谐。 PWM的应用又可以使用相关双采样（CDS）技术（通常限于离散时间电路）来提高有效dc增益。 PWM还允许使用有限运算放大器带宽补偿技术来节省功耗。提出并分析了CT调制器中的PWM调谐，CDS，抗混叠滤波，噪声和抖动分析，并通过大量仿真进行了验证。在0.18微米CMOS中级联2-2 DSM的原型CT上的测量结果表明，所提出的技术可以将调制器的动态范围（DR），SNDR和无杂散动态范围（SFDR）提高至少28 dB。第三，提出了一种高精度电容数字转换器（CDC），可以将其配置为与单端或差分电容传感器接口。在传统的CDC中，来自底板开关的电荷注入取决于数字输出和感测电容器的值。非线性尤其是在感测电容器的变化范围较大时引起。本文提出了新的开关和校准方案，以减少这些电荷注入。采用所提出技术的原型二阶CDC以0.18微米CMOS工艺制造，并在0.5ms的测量时间内实现了53.2aFrms的分辨率。所提出的技术将CDC的线性度在单端感测模式下从9.3位提高到12.3位，在差分感测模式下从10.1位提高到13.3位，感测电容范围从0.5到3.5pF。 CDC还通过实际的压力（单端）和加速度（微分）传感器进行了演示。

著录项

  • 作者

    Li, Bing.;

  • 作者单位

    The Chinese University of Hong Kong (Hong Kong).;

  • 授予单位 The Chinese University of Hong Kong (Hong Kong).;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2013
  • 页码 158 p.
  • 总页数 158
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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