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首页> 外文学位 >Static and dynamic nonlinearity compensation techniques for high performance current-steering digital-to-analog converters.
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Static and dynamic nonlinearity compensation techniques for high performance current-steering digital-to-analog converters.

机译：用于高性能电流控制数模转换器的静态和动态非线性补偿技术。

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摘要

High-speed high-accuracy digital-to-analog converters (DACs) are the crucial building blocks for many signal processing and telecommunication systems. The current-steering architecture is extensively used for these applications. With different decoding schemes--binary-weighted, unary-coded, and segment-coded, current-steering DACs are realized by groups of matched current sources. Their performance is limited by many nonlinear mechanisms such as random mismatch errors, gradient effect, code and voltage dependence of finite output impedance, nonlinear settling time, charge injection, and switch timing errors. In this thesis, two nonlinearity compensation techniques are presented to improve the overall performance of the current-steering DACs.;The first design technique is a novel digital calibration technique--complete-folding, which effectively compensates the random mismatch errors by selectively regrouping current sources into a fully binary-weighted array based on current comparisons after chip fabrication. The implementation only requires an analog current comparator and some digital circuitry. The minimum requirement of analog circuits makes complete-folding calibration suitable for DAC design in the low-voltage process. Statistical results with a behavioral model of a 14-bit segmented DAC in MATLAB show that complete-folding calibration can reduce the total gate area of current sources by a factor of almost 1200 compared to the DAC without using any calibration. Additional results also show that this new calibration technique has the superior performance in compensating random mismatch errors as compared to state-of-the-art.;The second design technique is a novel output impedance linearization technique that very effectively reduces the code and voltage dependence of finite output impedance. The linearization is achieved by using a small DAC switched with control signals opposite to those for the main DAC. The area and power overhead is less than 5% of the main DAC. Simulation results with a 14-bit segmented current-steering DAC in standard 0.18&mgr;m CMOS process show that the DAC's integral nonlinearity (INL) due to finite output impedance is improved by almost 5 bits. Additional results show that this technique is very robust to random mismatch errors. Moreover, not only the static linearity is improved, but most importantly there is a large dynamic linearity enhancement by output impedance linearization. Simulation results show that spurious-free dynamic range (SFDR) can be improved by almost 30 dB at the low signal frequencies and more than 8 dB for the high signal frequencies up to Nyquist rate while sampling at 500MS/s.
机译：高速高精度数模转换器（DAC）是许多信号处理和电信系统的关键组成部分。当前指导架构已广泛用于这些应用。采用不同的解码方案-二进制加权，一元编码和分段编码，电流控制DAC通过匹配的电流源组实现。它们的性能受到许多非线性机制的限制，例如随机失配误差，梯度效应，有限输出阻抗的代码和电压依赖性，非线性建立时间，电荷注入和开关时序误差。本文提出了两种非线性补偿技术来改善电流控制DAC的整体性能。第一种设计技术是一种新颖的数字校准技术-完全折叠，它可以通过选择性地重组电流来有效补偿随机失配误差。根据芯片制造后的电流比较，将信号源转换为完全二进制加权的阵列。该实现仅需要一个模拟电流比较器和一些数字电路。模拟电路的最低要求使得完整折叠校准适合于低压工艺中的DAC设计。用MATLAB中14位分段DAC的行为模型进行的统计结果表明，与不使用任何校准的DAC相比，完全折叠校准可以将电流源的总栅极面积减小近1200倍。附加结果还表明，与最新技术相比，这种新的校准技术在补偿随机失配误差方面具有卓越的性能。第二种设计技术是一种新颖的输出阻抗线性化技术，可以非常有效地降低编码和电压依赖性有限的输出阻抗。通过使用一个小型DAC来实现线性化，该小型DAC的控制信号与主DAC的控制信号相反。面积和功耗开销不到主DAC的5％。使用标准0.18μmCMOS工艺的14位分段电流控制DAC的仿真结果表明，由于有限的输出阻抗，DAC的积分非线性（INL）几乎提高了5位。其他结果表明，该技术对于随机失配误差非常可靠。此外，不仅改善了静态线性度，而且最重要的是通过输出阻抗线性化大大提高了动态线性度。仿真结果表明，在以500MS / s采样时，在低信号频率下无杂散动态范围（SFDR）可以提高近30 dB，在高达奈奎斯特速率的高信号频率下可以提高8 dB以上。

著录项

  • 作者

    Zeng, Tao.;

  • 作者单位

    Iowa State University.;

  • 授予单位 Iowa State University.;
  • 学科 Electrical engineering.
  • 学位 M.S.
  • 年度 2010
  • 页码 66 p.
  • 总页数 66
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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