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Application of VHDL-AMS to modeling and assessment of integrated circuit clock distribution networks.

机译：VHDL-AMS在集成电路时钟分配网络的建模和评估中的应用。

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摘要

In the past few decades, integrated circuit technology has been advancing rapidly. Clock distribution over an entire chip is a very complex problem and is one of the main challenges in the design of today's high-performance processors. The performance and functionality of the entire system depends on the clock characteristics. For a VLSI circuit, an accurate model of the clock distribution network is helpful for the precise performance evaluation of the system [1]. It will be of great help to the circuit designers to model uncertainties in the clock signal arrival times between key points in a clock distribution network.; In this thesis, we present an approach of using a mixed-signal Hardware Description Language (HDL) to model the characteristics of a clock distribution network. VHDL (Very High Speed Integrated Circuit HDL) is a widely used HDL for digital system modeling. For this research, an extension of VHDL called VHDL-AMS with Analog and Mixed Signal Modeling capabilities is used. A clock distribution network has components like Interconnects, Buffers, Phase Locked Loop, Source Oscillator, Delay locked loop, etc. In this research, a set of component models for Interconnects, Buffers and Phase locked loop are developed. Using these component models, a generic clock distribution network is modeled.; Two case studies are considered for experimentation. In the first case, an H-Tree clock distribution network is modeled and the variation of skew across the levels of H-Tree is studied. In the second case, a regular pattern clock distribution network is modeled and the variation of skew for varying interconnect lengths, load capacitance and the number of stages in a regular pattern clock distribution network is analyzed. The results are also validated with SPICE.
机译：在过去的几十年中，集成电路技术一直在迅速发展。整个芯片上的时钟分配是一个非常复杂的问题，并且是当今高性能处理器设计中的主要挑战之一。整个系统的性能和功能取决于时钟特性。对于VLSI电路，时钟分配网络的准确模型有助于系统的精确性能评估[1]。对电路设计者来说，对时钟分配网络中关键点之间的时钟信号到达时间的不确定性建模将有很大的帮助。在本文中，我们提出了一种使用混合信号硬件描述语言（HDL）对时钟分配网络的特征进行建模的方法。 VHDL（超高速集成电路HDL）是一种广泛用于数字系统建模的HDL。对于本研究，使用了具有模拟和混合信号建模功能的VHDL扩展，称为VHDL-AMS。时钟分配网络具有互连，缓冲器，锁相环，源振荡器，延迟锁定环等组件。在本研究中，开发了一组互连，缓冲器和锁相环组件模型。使用这些组件模型，可以对通用时钟分配网络进行建模。考虑两个案例研究进行实验。在第一种情况下，对H-Tree时钟分配网络进行建模，并研究H-Tree各个级别上的时滞变化。在第二种情况下，对常规模式时钟分配网络进行建模，并分析常规模式时钟分配网络中互连长度，负载电容和级数变化时的偏斜变化。结果也用SPICE验证。

著录项

  • 作者

    Kandula, Sireesha.;

  • 作者单位

    University of Cincinnati.;

  • 授予单位 University of Cincinnati.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 M.S.
  • 年度 2005
  • 页码 122 p.
  • 总页数 122
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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