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Characterization and avoidance of critical pipeline structures in aggressive superscalar processors.

机译：表征和避免攻击性超标量处理器中的关键管线结构。

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In recent years, with only small fractions of modern processors now accessible in a single cycle, computer architects constantly fight against propagation issues across the die. Unfortunately this trend continues to shift inward, and now the even most internal features of the pipeline are designed around communication, not computation. To address the inward creep of this constraint, this work focuses on the characterization of communication within the pipeline itself, architectural techniques to avoid it when possible, and layout co-design for early detection of problems. I present work in creating a novel detection tool for common case operand movement which can rapidly characterize an application's dataflow patterns. The results produced are suitable for exploitation as a small number of patterns can describe a significant portion of modern applications. Work on dynamic dependence collapsing takes the observations from the pattern results and shows how certain groups of operations can be dynamically grouped, avoiding unnecessary communication between individual instructions. This technique also amplifies the efficiency of pipeline data structures such as the reorder buffer, increasing both IPC and frequency. I also identify the same sets of collapsible instructions at compile time, producing the same benefits with minimal hardware complexity. This technique is also done in a backward compatible manner as the groups are exposed by simple reordering of the binary's instructions. I present aggressive pipelining approaches for these resources which avoids the critical timing often presumed necessary in aggressive superscalar processors. As these structures are designed for the worst case, pipelining them can produce greater frequency benefit than IPC loss. I also use the observation that the dynamic issue order for instructions in aggressive superscalar processors is predictable. Thus, a hardware mechanism is introduced for caching the wakeup order for groups of instructions efficiently. These wakeup vectors are then used to speculatively schedule instructions, avoiding the dynamic scheduling when it is not necessary. Finally, I present a novel approach to fast and high-quality chip layout. By allowing architects to quickly evaluate 'what if' scenarios during early high-level design, chip designs are less likely to encounter implementation problems later in the process.
机译：近年来，由于现在只有一小部分现代处理器可以在一个周期内访问，因此计算机架构师一直在与芯片之间的传播问题作斗争。不幸的是，这种趋势继续向内转移，现在管道的大多数内部功能都是围绕通信而不是计算来设计的。为了解决此约束的内向蠕变问题，这项工作着重于管道本身内的通信特性，在可能的情况下避免使用的体系结构技术以及用于及早发现问题的布局协同设计。我介绍了创建用于常见情况操作数移动的新颖检测工具的工作，该工具可以快速表征应用程序的数据流模式。产生的结果适合于开发，因为少量模式可以描述现代应用程序的很大一部分。动态依赖折叠的工作从模式结果中获取观察结果，并显示了如何将某些操作组动态分组，从而避免了各个指令之间不必要的通信。该技术还提高了流水线数据结构（例如重排序缓冲区）的效率，同时提高了IPC和频率。我还将在编译时识别相同的可折叠指令集，从而以最小的硬件复杂性产生相同的好处。当组通过二进制指令的简单重新排序公开时，该技术也以向后兼容的方式完成。我为这些资源提供了积极的流水线方法，避免了通常认为在积极的超标量处理器中必需的关键时序。由于这些结构是为最坏的情况设计的，因此对它们进行流水线化可产生比IPC损耗更大的频率优势。我还观察到，积极的超标量处理器中指令的动态发布顺序是可以预测的。因此，引入了一种硬件机制，用于有效地缓存指令组的唤醒顺序。然后将这些唤醒向量用于推测性调度指令，避免在不必要时进行动态调度。最后，我提出了一种新颖的方法来实现快速，高质量的芯片布局。通过允许架构师在早期高级设计中快速评估“假设情况”，芯片设计在此过程的后期不太可能遇到实施问题。

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