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An Ultra-Low-Energy, Variation-Tolerant FPGA Architecture Using Component-Specific Mapping.

机译：使用特定于组件的映射的超低功耗，耐变化的FPGA架构。

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摘要

As feature sizes scale toward atomic limits, parameter variation continues to increase, leading to increased margins in both delay and energy. Parameter variation both slows down devices and causes devices to fail. For applications that require high performance, the possibility of very slow devices on critical paths forces designers to reduce clock speed in order to meet timing. For an important and emerging class of applications that target energy-minimal operation at the cost of delay, the impact of variation-induced defects at very low voltages mandates the sizing up of transistors and operation at higher voltages to maintain functionality.;With post-fabrication configurability, FPGAs have the opportunity to self-measure the impact of variation, determining the speed and functionality of each individual resource. Given that information, a delay-aware router can use slow devices on non-critical paths, fast devices on critical paths, and avoid known defects. By mapping each component individually and customizing designs to a component's unique physical characteristics, we demonstrate that we can eliminate delay margins and reduce energy margins caused by variation.;To quantify the potential benefit we might gain from component-specific mapping, we first measure the margins associated with parameter variation, and then focus primarily on the energy benefits of FPGA delay-aware routing over a wide range of predictive technologies (45 nm–12 nm) for the Toronto20 benchmark set. We show that relative to delay-oblivious routing, delay-aware routing without any significant optimizations can reduce minimum energy/operation by 1.72× at 22 nm. We demonstrate how to construct an FPGA architecture specifically tailored to further increase the minimum energy savings of component-specific mapping by using the following techniques: power gating, gate sizing, interconnect sparing, and LUT remapping. With all optimizations considered we show a minimum energy/operation savings of 2.66× at 22 nm, or 1.68–2.95× when considered across 45–12 nm. As there are many challenges to measuring resource delays and mapping per chip, we discuss methods that may make component-specific mapping more practical. We demonstrate that a simpler, defect-aware routing achieves 70% of the energy savings of delay-aware routing. Finally, we show that without variation tolerance, scaling from 16 nm to 12 nm results in a net increase in minimum energy/operation; component-specific mapping, however, can extend minimum energy/operation scaling to 12 nm and possibly beyond.
机译：随着特征尺寸朝原子极限方向扩展，参数变化继续增加，从而导致延迟和能量的裕度增加。参数变化既会降低设备速度，又会导致设备故障。对于需要高性能的应用，关键路径上非常慢的器件的可能性迫使设计人员降低时钟速度以满足时序要求。对于以能量消耗最小化为代价以延迟为目标的重要且新兴的应用类别，在非常低的电压下因变化引起的缺陷的影响要求对晶体管进行尺寸调整，并在更高的电压下进行操作以保持功能。在制造可配置性方面，FPGA有机会自测变化的影响，确定每个单独资源的速度和功能。有了这些信息，延迟感知路由器可以在非关键路径上使用慢速设备，在关键路径上使用快速设备，并避免已知的缺陷。通过分别映射每个组件并根据组件的独特物理特性进行定制设计，我们证明了我们可以消除延迟裕量并减少由变化引起的能量裕量。为了量化我们可以从特定于组件的映射中获得的潜在利益，我们首先测量与参数变化相关的余量，然后主要集中在针对Toronto20基准测试集的广泛预测技术（45 nm至12 nm）上的FPGA延迟感知路由的能量收益。我们表明，相对于无延迟的路由，无任何明显优化的延迟感知路由可以在22 nm处将最小能量/工作量减少1.72倍。我们演示了如何使用以下技术构建专门为进一步提高特定组件映射的最低能耗而量身定制的FPGA架构：电源门控，门选型，互连备用和LUT重新映射。考虑到所有优化，我们显示出在22 nm处的最小能量/操作节省为2.66倍，而在45-12 nm处考虑的最小能量/操作节省为1.68–2.95倍。由于测量资源延迟和每个芯片的映射存在许多挑战，因此我们讨论了使特定于组件的映射更加实用的方法。我们证明了一种更简单的，可感知缺陷的路由可节省70％的可感知延迟路由的能源。最后，我们表明，在没有变化容差的情况下，从16 nm缩放到12 nm会导致最小能量/操作的净增加；但是，特定于组件的映射可以将最小的能量/操作缩放比例扩展到12 nm，甚至可能更大。

著录项

  • 作者

    Mehta, Nikil.;

  • 作者单位

    California Institute of Technology.;

  • 授予单位 California Institute of Technology.;
  • 学科 Engineering Computer.;Computer Science.;Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2013
  • 页码 133 p.
  • 总页数 133
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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