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Design and Implementation of Networkds-on-Chip: A Cost-Efficient Framwork.

机译：片上网络的设计和实现：一种经济高效的框架。

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摘要

Integrating many processing elements (PE) in a single chip is inevitable as silicon technology allows more than one billion of transistors in a single piece of silicon. Networks-on-Chip (NoCs) has been proposed as a scalable solution to both increasing bandwidth requirements and physical design problems for multi-PE chips. However, as multi-PE chips drive the design focus to shift from the computation-centric to communication-centric, area and power costs consumed by communication has become comparable to what computation consumes.;The second direction is to reduce hop counts of packets when they travel from sources to destinations, and thus to reduce power consumption of NoCs. The reduction of hop counts is realized by using a recently proposed express virtual channel (EVC) technique to virtually bypass intermediate routers. We study the EVC technique in two domains. The first domain is to present a high-level, application-specific methodology to improve power efficiency of EVC paths early in the design stage. The methodology includes three steps. Firstly, aggregate communication loads between routers are calculated. Secondly, an energy reduction model and an energy overhead model are developed. Finally, energy savings of all possible EVCs path are calculated and a greedy algorithm is applied to insert EVCs paths in an iterative way.;The second domain is to exploit the EVC flow control in design and implementation of low-power NoCs. We firstly present cost-efficient hardware components for both EVC source and EVC bypass routers, then propose a statistical approach to customize buffer architectures for EVC networks, then describe creative use of low-power circuit techniques such as clock gating and operand isolation for EVC routers, and finally evaluate EVC NoCs through detailed ASIC implementations. Results show that EVC NoCs can save up to 34.26% of power compared to baseline NoCs.;This thesis tackles design and implementation of cost-efficient NoCs along two orthogonal directions. The first direction is to reduce area and power costs of a single virtual channel router. Through ASIC implementations, we find that allocator logic, including both virtual channel allocator (VA) and switch allocator (SA), consumes a large amount of costs. Based on RTL simulations for the entire NoCs, we identify great opportunities to reduce design costs of VA and then propose two low-complexity allocators: look-ahead VA and combined switch-VC allocator (SVA). Evaluations are performed for a wide range of traffic patterns and router parameters. Results show that both proposed architectures significantly reduce area and power costs of allocators without penalties on network performances.
机译：由于硅技术允许在单个硅片中使用超过十亿个晶体管，因此在单个芯片中集成许多处理元件（PE）是不可避免的。片上网络（NoCs）已被提出作为可扩展的解决方案，以解决带宽需求增加和多PE芯片的物理设计问题。但是，随着多PE芯片驱动设计重点从以计算为中心转移到以通信为中心，通信所消耗的面积和功率成本已变得可与计算所消耗的成本相提并论;第二个方向是减少数据包的跳数它们从源头到目的地，从而降低了NoC的功耗。跳数的减少是通过使用最近提出的快速虚拟通道（EVC）技术虚拟绕过中间路由器来实现的。我们在两个领域研究EVC技术。第一个领域是提出一种高级的，特定于应用程序的方法，以在设计阶段的早期提高EVC路径的功率效率。该方法包括三个步骤。首先，计算路由器之间的总通信负载。其次，建立了节能模型和能耗模型。最后，计算了所有可能的EVC路径的节能量，并采用贪婪算法以迭代方式插入EVC路径。第二个领域是在低功耗NoC的设计和实现中利用EVC流控制。我们首先介绍用于EVC源和EVC旁路路由器的具有成本效益的硬件组件，然后提出一种统计方法来为EVC网络定制缓冲区架构，然后描述对EVC路由器的低功耗电路技术（如时钟门控和操作数隔离）的创造性使用，最后通过详细的ASIC实现评估EVC NoC。结果表明，与基线NoC相比，EVC NoC最多可节省34.26％的功耗。；本文针对两个正交方向上具有成本效益的NoC进行设计和实现。第一个方向是减少单个虚拟通道路由器的面积和电源成本。通过ASIC实现，我们发现分配器逻辑（包括虚拟通道分配器（VA）和交换器分配器（SA））消耗大量成本。基于整个NoC的RTL仿真，我们发现了降低VA设计成本的巨大机会，然后提出了两种低复杂度的分配器：超前VA和组合式VC分配器（SVA）。对各种流量模式和路由器参数进行评估。结果表明，两种提议的体系结构都可以显着减少分配器的面积和电源成本，而不会影响网络性能。

著录项

  • 作者

    Zhang, Min.;

  • 作者单位

    The Chinese University of Hong Kong (Hong Kong).;

  • 授予单位 The Chinese University of Hong Kong (Hong Kong).;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2010
  • 页码 145 p.
  • 总页数 145
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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