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An 11-bit 20MS/s Pipelined Analog-to-Digital Converter with Op Amp Sharing.

机译：具有运算放大器共享的11位20MS / s流水线模数转换器。

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In today's System-on-Chip (SoC) design, both analog and digital circuits play important role. Digital circuits are fully used to build memory and signal processing blocks. With technology scaling, speed of digital circuits has been boosted a lot in deep submicron technologies. Being the interface between real world and digital block, Analog-to-Digital Converter (ADC) is now very critical. Since high speed and high precision is required, ADC has now become a bottleneck in SoC design. Especially when integrated with digital circuits, ADC has to maintain its performance in noisy environment. Therefore, effort is deserved to develop high resolution, low power ADC designs.;In this thesis, an 11-bit Pipelined ADC with Op Amp sharing technique is presented. The post-layout simulation shows an SNDR of 59.46dB and SFDR of 69.00dB. Current consumption is around 11mA from 2.5V power supply.

机译：在当今的片上系统（SoC）设计中，模拟电路和数字电路都起着重要的作用。数字电路完全用于构建存储器和信号处理模块。随着技术的扩展，在深亚微米技术中，数字电路的速度已大大提高。作为现实世界和数字模块之间的接口，模数转换器（ADC）现在非常重要。由于需要高速和高精度，因此ADC现在已成为SoC设计的瓶颈。特别是当与数字电路集成时，ADC必须在嘈杂的环境中保持其性能。因此，应致力于开发高分辨率，低功耗的ADC设计。本文提出了一种采用运算放大器共享技术的11位流水线ADC。布局后仿真显示SNDR为59.46dB，SFDR为69.00dB。 2.5V电源消耗的电流约为11mA。

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作者
Kong, Long.;
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作者单位

University of California, Los Angeles.;

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授予单位 University of California, Los Angeles.;
学科 Engineering Electronics and Electrical.
学位 M.S.
年度 2013
页码 72 p.
总页数 72
原文格式 PDF
正文语种 eng
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专利

1. A pseudo-differential current-reuse structure for opamp-sharing pipelined analog-to-digital converters [J] . Moosazadeh Tohid, Yavari Mohammad International journal of circuit theory and applications . 2015,第7期

机译：用于运算放大器共享流水线模数转换器的伪差分电流复用结构
2. A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters [J] . Hwi-Cheol Kim, Deog-Kyoon Jeong, Kim W. IEEE transactions on circuits and systems . I , Regular papers . 2006,第4期

机译：高速低功耗流水线模数转换器的部分开关运算技术
3. A Partially Switched-Opamp Technique for High-Speed Low-Power Pipelined Analog-to-Digital Converters [J] . Hwi-Cheol Kim, Deog-Kyoon Jeong, Wonchan Kim IEEE Transactions on Circuits and Systems. I, Regular Papers . 2006,第4期

机译：高速低功耗流水线模数转换器的部分开关运算技术
4. Operational amplifier design for high-speed pipelined Analog-to-Digital Converters in deep-submicron CMOS processes [C] . Nieminen Tero, Halonen Kari 2011 7th Conference on Ph.D. Research in Microelectronics and Electronics . 2011

机译：用于深亚微米CMOS工艺的高速流水线模数转换器的运算放大器设计
5. A 12-bit, 40 msamples/s, low-power, low-area pipeline analog-to-digital converter in CMOS 0.18 mum technology. [D] . Mohajerin, Mani. 2004

机译：采用CMOS 0.18毫米技术的12位，40 msamples / s，低功耗，低面积流水线模数转换器。
6. Bias Controller of Mach–Zehnder Modulator for Electro-Optic Analog-to-Digital Converter [O] . Shuxin Shi, Jun Yuan, Qin Huang, 2019

机译：电光模数转换器Mach–Zehnder调制器的偏置控制器
7. 10-bit 40MHZ Sampling Rate Pipelined Analog-to-Digital Converter [O] . 孙志新 2011

机译：10位40MHZ采样率流水线模数转换器

An 11-bit 20MS/s Pipelined Analog-to-Digital Converter with Op Amp Sharing.

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