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Electrostatic discharge and electrical overstress failures of non-silicon devices.

机译：非硅器件的静电放电和电气过应力故障。

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摘要

Electrostatic discharge (ESD) causes a significant percentage of the failures in the electronics industry. The shrinking size of semiconductor circuits, thinner gate oxides, complex chips with multiple power supplies and mixed-signal blocks, larger chip capacitance and faster circuit operation, all contribute to increased ESD sensitivity of advanced semiconductor devices. Therefore, understanding and controlling ESD is indispensable for higher quality and reliability of advanced device technologies.; This thesis provides a comprehensive understanding of ESD and EOS failures in GaAs and SiGe devices. In the first part of this thesis, characteristics of internal damage caused by several ESD test models and EOS stress in non-silicon devices (GaAs and SiGe) are identified. Failure signatures are correlated with field failures using various failure analysis techniques.; The second part of this thesis discusses the effects of ESD latent damage in GaAs devices. Depending on the stress level, ESD voltage can causes latent failures if the device is repeatedly stressed under low ESD voltage conditions, and can cause premature damage leading eventually to catastrophic failures. Electrical degradation due to ESD-induced latent damage in GaAs MESFETs after cumulative low-level ESD stress is studied. Using failure analysis, combined with electrical characterization, the failure modes and signatures of EOS stressed devices with and without prior low-level ESD stress are compared.; To predict the power-to-failure level of GaAs and silicon devices, an ESD failure model using a thermal RC network was developed. A correlation method of the real ESD stress and square wave pulse has been developed. The equivalent duration of the square pulse is calculated and proposed for the HBM ESD stress. The dependence of this value on the ESD stress level and material properties is presented as well.
机译：静电放电（ESD）导致电子行业中很大比例的故障。半导体电路尺寸的缩小，更薄的栅极氧化物，具有多个电源和混合信号块的复杂芯片，更大的芯片电容和更快的电路操作，均有助于提高高级半导体器件的ESD灵敏度。因此，了解和控制ESD对于先进设备技术的更高质量和可靠性是必不可少的。本文全面了解了GaAs和SiGe器件中的ESD和EOS故障。在本文的第一部分中，确定了由几种ESD测试模型和非硅器件（GaAs和SiGe）中EOS应力引起的内部损坏的特征。使用各种故障分析技术将故障签名与现场故障关联起来。本文的第二部分讨论了GaAs器件中ESD潜在损坏的影响。根据应力水平，如果在低ESD电压条件下反复施加压力，ESD电压可能会导致潜在故障，并可能导致过早损坏，最终导致灾难性故障。研究了在累积的低电平ESD应力之后，由于ESD引起的GaAs MESFET潜在潜能损伤引起的电性能下降。使用故障分析并结合电气特性，比较了有无早期ESD应力的EOS应力器件的失效模式和特征。为了预测GaAs和硅器件的电源到故障水平，开发了使用热RC网络的ESD故障模型。研究了实际ESD应力与方波脉冲的相关方法。计算平方脉冲的等效持续时间，并针对HBM ESD应力提出建议。还介绍了该值对ESD应力水平和材料性能的依赖性。

著录项

  • 作者

    Hwang, Yu-Chul.;

  • 作者单位

    University of Maryland, College Park.;

  • 授予单位 University of Maryland, College Park.;
  • 学科 Engineering Mechanical.
  • 学位 Ph.D.
  • 年度 2005
  • 页码 134 p.
  • 总页数 134
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 机械、仪表工业;
  • 关键词

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