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Enhanced scan architectures for improving test application time and power.

机译：增强的扫描架构，可改善测试应用程序的时间和功能。

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摘要

Shrinkage of feature size allows future system-on-chip (SOC) to have various types of digital and analog IP cores. Each IP typically has different native testing requirements and design for tests (DFTs). Generally, DFTs reduce cost by reducing the I/O data rate requirements, low pin count for testing and less expensive test equipments. But, the DFTs, such as scan and BIST, for such designs are very limited and requires considerable research to avoid high cost test equipments for testing such complex designs. In other words, every IP core must be tested in a serial fashion that, in turn, results in longer test time and higher manufacturing costs. DFT based test approaches require innovative solutions to improve application time and power consumption of today's SoC testing. Scan is the most accepted DFT in industry for core-based testing due to its improved controlability and observability compared to other DFTs such as BIST. In this work, we are focused on scan architectures (e.g. full scan, scan-based BIST and boundary scan) to alleviate some of the today's SoC testing challenges.;We propose two data compression techniques called run-length Huffman (RL-Huffman) and nine-coded (9C). RL-Huffman, which is a data-dependent technique, produces high compression and significantly reduces the test application time for scan designs. It also minimizes scan-in power consumption during test application. It uses two well known encoding techniques, RL and Huffman, to compress the test data set. The second technique, 9C, is a data-independent technique with a very small decoder providing high compression ratio and also reduces the power consumption during test.;We also propose a new low power test pattern generator using linear feedback shift register, called LP-LFSR, to reduce the switching activity in a circuit under test. LP-LFSR increases the correlation between the test patterns which eventually reduces the switching activity in the primary inputs and circuit under test. This technique is very cost effective compared to the other proposed techniques and effectively reduces the peak and average power. Our experimental results on the ISCAS benchmarks indicate that LP-LFSR not only decreases power but also reduces the test time while conventional techniques can only reduce power with the expense of test time.;And finally, we also explore signal integrity fault modeling, test pattern generation and extending boundary scan to generate the test patterns and observe the test responses. In this work, we enhance boundary scan cells to generate our proposed signal integrity test patterns and apply them onto the interconnects under test. New cells also have been proposed to observe signal integrity faults. Two new optional instructions are proposed for test pattern generation and scanning out the test responses, respectively. On-chip pattern generation and application on SoC interconnects significantly reduces the test application time as the total number of long interconnects in an SoC is increasing.
机译：功能尺寸的缩小允许未来的片上系统（SOC）具有各种类型的数字和模拟IP内核。每个IP通常具有不同的本机测试要求和测试设计（DFT）。通常，DFT通过降低I / O数据速率要求，用于测试的引脚数少和价格便宜的测试设备来降低成本。但是，用于此类设计的DFT（例如扫描和BIST）非常有限，需要大量研究才能避免使用昂贵的测试设备来测试这种复杂的设计。换句话说，必须以串行方式对每个IP内核进行测试，从而导致更长的测试时间和更高的制造成本。基于DFT的测试方法需要创新的解决方案，以缩短当今SoC测试的应用时间和功耗。与基于BIST的其他DFT相比，Scan具有更好的可控制性和可观察性，因此它是业界针对基于核心的测试最受接受的DFT。在这项工作中，我们专注于扫描架构（例如全扫描，基于扫描的BIST和边界扫描），以缓解当今SoC测试中的一些挑战。我们提出了两种数据压缩技术，称为游程长度霍夫曼（RL-Huffman）和九码（9C）。 RL-Huffman是一种与数据相关的技术，可产生很高的压缩率并显着减少扫描设计的测试应用时间。它还可以最大程度地减少测试应用过程中的扫描输入功耗。它使用两种众所周知的编码技术RL和Huffman来压缩测试数据集。第二种技术是9C，它是一种与数据无关的技术，其解码器非常小，具有很高的压缩率，并且可以降低测试过程中的功耗。我们还提出了一种新的使用线性反馈移位寄存器的低功耗测试码型发生器，称为LP- LFSR，以减少被测电路的开关活动。 LP-LFSR增加了测试模式之间的相关性，最终降低了主要输入和被测电路中的开关活动。与其他提议的技术相比，该技术非常具有成本效益，并有效地降低了峰值功率和平均功率。我们在ISCAS基准上的实验结果表明，LP-LFSR不仅可以降低功率，而且可以减少测试时间，而传统技术只能以测试时间为代价来降低功率。最后，我们还探讨了信号完整性故障建模，测试模式生成和扩展边界扫描以生成测试图案并观察测试响应。在这项工作中，我们增强了边界扫描单元，以生成我们提出的信号完整性测试模式，并将其应用于测试中的互连。还提出了新的电池来观察信号完整性故障。提出了两个新的可选指令，分别用于生成测试模式和扫描出测试响应。随着SoC中长互连的总数不断增加，片上模式生成和在SoC互连上的应用大大减少了测试应用时间。

著录项

  • 作者

    Tehranipoor, Mohammad H.;

  • 作者单位

    The University of Texas at Dallas.;

  • 授予单位 The University of Texas at Dallas.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2004
  • 页码 169 p.
  • 总页数 169
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 康复医学;
  • 关键词

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