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A 600 mega-sample/sec 8-bit ADC in 0.18mum CMOS.

机译：一个0.18mm CMOS的600兆采样/秒的8位ADC。

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摘要

The rapid advancement of digital signal processing and the thrust to digitize analog signals at radio frequencies impose stringent requirements on high speed ADCs as a crucial component to interface between the analog and digital domains.; With the fast scaling of semiconductor technology, the lower supply voltage has become an inevitable trend for modern ULSIs. The integration of analog and digital circuits on the same chip and operating under the same supply voltage has the major advantage in reducing the overall system cost. This enforces the development of low power supply ADCs.; The main design issues for such high speed and low power supply ADCs include switching related errors, static and dynamic offsets, low dynamic range operation and difficult gain-bandwidth optimization. Design trade-offs among power, speed and chip area are further tightened with the super-scaled CMOS process.; This dissertation presents a detailed design methodology for developing a 600 Mega-Sample/Sec 8-bit ADC in CMOS, which adopts the folding and interpolation architecture to reduce the power consumption and total component number. The distributed Track/Holds (T/Hs) are applied to reduce the design constraints on individual T/H. Capacitor averaging network is uniquely embedded in distributed T/Hs to reduced the random switching errors. Boundary zero crossing shift problem in folding-interpolation network is carefully analyzed and the dummy zero crossings are applied to mitigate this problem. High efficient digital error correction logic is designed to reduce errors caused by the mismatch between the coarse and fine channels in folding ADC.; Fabricated in a 0.18mum 1P6M CMOS technology, the prototype ADC occupies an active area of 0.5 mm2. The whole ADC consumes 207mW with a single 1.8V supply while operating at 600MHz conversion rate with input signal frequencies up to 205 MHz. The measured peak DNL and INL are recorded as 0.6 LSB and 0.9 LSB, respectively. Near the Nyquist input frequencies, the SNDR always maintains above 39dB. With fixed input frequency of 55MHz, the SNDR can actually sustain at 40dB with clock frequencies up to 1GHz.
机译：数字信号处理的迅速发展以及对射频模拟信号进行数字化的努力，对高速ADC提出了严格的要求，因为高速ADC是模拟域和数字域之间接口的重要组成部分。随着半导体技术的快速发展，较低的电源电压已成为现代ULSI的必然趋势。将模拟和数字电路集成在同一芯片上并在相同的电源电压下运行具有降低整体系统成本的主要优势。这迫使开发低功耗ADC。这种高速，低功耗ADC的主要设计问题包括与开关相关的误差，静态和动态失调，低动态范围操作以及困难的增益带宽优化。通过超大规模CMOS工艺，功率，速度和芯片面积之间的设计权衡得到了进一步加强。本文提出了一种详细的设计方法，用于开发采用CMOS的600 Mega-Sample / Sec 8位ADC，该ADC采用折叠和插值架构以减少功耗和总元件数。应用分布式跟踪/保持（T / Hs）可以减少对单个T / H的设计约束。电容器平均网络独特地嵌入在分布式T / H中，以减少随机切换误差。仔细分析了折叠插值网络中的边界零交叉漂移问题，并采用了虚拟零交叉来缓解这一问题。高效的数字错误校正逻辑旨在减少折叠ADC中粗通道和精通道之间的不匹配引起的错误。 ADC采用0.18mum 1P6M CMOS技术制造，有效面积为0.5 mm2。整个ADC用1.8V单电源消耗207mW的功率，同时以600MHz的转换速率工作，输入信号频率高达205MHz。测得的峰值DNL和INL分别记录为0.6 LSB和0.9 LSB。在奈奎斯特输入频率附近，SNDR始终保持在39dB以上。在55MHz的固定输入频率下，SNDR实际上可以在时钟频率高达1GHz的情况下维持在40dB。

著录项

  • 作者

    Wang, Zhengyu.;

  • 作者单位

    University of California, Los Angeles.;

  • 授予单位 University of California, Los Angeles.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2004
  • 页码 89 p.
  • 总页数 89
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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