• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文学位 >Systematic exploration of trade-offs between application throughput and hardware resource requirements in DSP systems.
【24h】

Systematic exploration of trade-offs between application throughput and hardware resource requirements in DSP systems.

机译：系统研究DSP系统中应用程序吞吐量和硬件资源需求之间的折衷。

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Dataflow has been used extensively as an efficient model-of-computation to analyze performance and resource requirements in implementing DSP algorithms on various target architectures. Although various software synthesis techniques have been widely studied in recent years, there is a distinct lack of efficient synthesis techniques in the literature for systematically mapping dataflow models into efficient hardware implementations. In this thesis, we explore three different aspects that contribute to the development of a powerful dataflow-based hardware synthesis framework: (1) Systematic generation of 1D/2D FFT implementation on field programmable gate arrays (FPGAs). The fast Fourier transform (FFT) is one of the most widely-used and important signal processing functions. However, FFT computation generally becomes a major bottleneck for overall system performance due to its high computational requirements. We propose a systematic approach for synthesizing FPGA implementations of one- and two-dimensional (1D and 2D) FFT computations, and rigorously exploring trade-offs between cost (in terms of FPGA resource requirements) and performance (in terms of throughput). Our approach provides an efficient hardware synthesis framework that can be customized to specific design constraints. In our FFT synthesis approach, we apply two orthogonal techniques in FPGA implementation to realize data-parallelism and parallel processing in FFT computation, respectively. These techniques can be applied to various 1D FFT algorithms, including Radix-2 and Radix-4 algorithms, and extended naturally and efficiently to 2D FFT implementation. (2) Buffer optimization under self-timed execution. Self-timed execution is known to provide the maximum achievable throughput when mapping DSP dataflow graphs into hardware under certain technical constraints. Throughput-constrained buffer minimization under self-timed execution is a key question in efficient hardware synthesis for practical design scenarios. Previous approaches to this problem have suffered from high worst case complexity or loose buffer bounds, which lead to inefficient resource utilization. In this thesis, we integrate a novel constraint into traditional self-timed execution to obtain a modified form of self-timed execution, which we call MSTE (Modified Self-Timed Execution). We show that MSTE greatly improves the efficiency with which we can accurately analyze and optimize hardware configurations of dataflow graphs, and furthermore, the additional execution constraints imposed in MSTE result in relatively minor performance overhead. Based on MSTE, we explore novel methods for self-timed analysis and associated techniques for buffer optimization subject to given throughput constraints. (3) Hardware synthesis technique for parameterized dataflow model. Parameterized dataflow modeling approaches allow for dynamic capabilities without excessively compromising the key properties of the existing static dataflow model---compile-time predictability and potential for rigorous optimizations. We develop a novel PSDF-based FPGA architecture framework using National Instrument's LabVIEW FPGA, a recently-introduced commercial platform for reconfigurable hardware implementation. This framework develops novel connections among model-based DSP system design, FPGA implementation, and next generation wireless communication systems.
机译：数据流已广泛用作一种有效的计算模型，以分析在各种目标体系结构上实现DSP算法时的性能和资源需求。尽管近年来已经广泛研究了各种软件综合技术，但是文献中仍然缺乏有效的综合技术，无法将数据流模型系统地映射到有效的硬件实现中。在本文中，我们探讨了有助于开发基于数据流的强大硬件综合框架的三个不同方面：（1）在现场可编程门阵列（FPGA）上系统生成1D / 2D FFT实现。快速傅立叶变换（FFT）是最广泛使用且最重要的信号处理功能之一。但是，由于FFT计算量大，因此通常成为整个系统性能的主要瓶颈。我们提出一种系统化的方法，用于合成一维和二维（一维和二维）FFT计算的FPGA实现，并严格探索成本（就FPGA资源需求而言）和性能（就吞吐量而言）之间的取舍。我们的方法提供了可以针对特定设计约束进行定制的高效硬件综合框架。在我们的FFT综合方法中，我们在FPGA实现中应用了两种正交技术，分别在FFT计算中实现数据并行和并行处理。这些技术可以应用于包括Radix-2和Radix-4算法在内的各种1D FFT算法，并且自然而有效地扩展到2D FFT实现。 （2）自定时执行下的缓冲区优化。在某些技术约束下，将DSP数据流图映射到硬件时，自定时执行可提供最大的吞吐量。自定时执行下的吞吐量受限的缓冲区最小化是针对实际设计方案进行有效硬件综合的关键问题。解决该问题的先前方法遭受了最坏情况下的高复杂性或缓冲区边界的松动，这导致资源利用效率低下。在本文中，我们将一种新颖的约束条件整合到传统的自定时执行中，以获得一种修改后的自定时执行形式，我们称之为MSTE（修改后的自定时执行）。我们表明，MSTE大大提高了我们可以准确分析和优化数据流图的硬件配置的效率，此外，MSTE中施加的其他执行约束导致性能开销相对较小。在MSTE的基础上，我们探索了在给定吞吐量约束下用于自定时分析的新方法以及用于缓冲区优化的相关技术。 （3）参数化数据流模型的硬件综合技术。参数化数据流建模方法可实现动态功能，而不会过度损害现有静态数据流模型的关键特性-编译时的可预测性和进行严格优化的潜力。我们使用National Instruments的LabVIEW FPGA开发了基于PSDF的新颖FPGA架构框架，这是最近引入的用于可重配置硬件实现的商业平台。该框架在基于模型的DSP系统设计，FPGA实现和下一代无线通信系统之间建立了新颖的联系。

著录项

  • 作者

    Kee, Hojin.;

  • 作者单位

    University of Maryland, College Park.;

  • 授予单位 University of Maryland, College Park.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2010
  • 页码 129 p.
  • 总页数 129
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号