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A high-speed two-step analog-to-digital converter with an open-loop residue amplifier.

机译：具有开环残差放大器的高速两步式模数转换器。

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摘要

With the revolution of the digital CMOS design, the CMOS technology has become the dominant process technology in today's semiconductor industry. However, as the channel lengths of the MOS transistors reduce with the introduction of each CMOS process node, the intrinsic gain (gm x rds) of the MOS transistors decreases. As this trend continues, the high-gain amplifiers required for accurate residue amplification in pipelined ADCs will not have enough open-loop gain to provide sufficient accuracy. Therefore, achievable accuracy or speed must be lowered. On the other hand, new circuit architectures and clever use of the readily available powerful DSP capability can be exploited to decouple the gain, accuracy, and speed requirements.;The main objective of this research was to develop a background calibration technique that would enable the design of a 2-stage pipelined ADC with an open-loop residue amplifier. This technique and its variations can potentially eliminate the need for high-gain amplifiers in pipelined ADCs, which is especially vital for high-performance ADC design in modern fine-line CMOS technologies.;Moreover, a double-switching switched-buffer SHA architecture was proposed and demonstrated. The proposed double-switching architecture eliminates the hold-mode feed-through. Therefore, the SHA maintains its linearity with input frequencies as high as the Nyquist rate.
机译：随着数字CMOS设计的革命，CMOS技术已成为当今半导体行业的主导工艺技术。然而，随着MOS晶体管的沟道长度随着每个CMOS处理节点的引入而减小，MOS晶体管的固有增益（gm×rds）减小。随着这种趋势的继续，流水线ADC中精确残差放大所需的高增益放大器将没有足够的开环增益来提供足够的精度。因此，必须降低可达到的精度或速度。另一方面，可以利用新的电路架构和对现成的强大DSP功能的巧妙使用来解耦增益，精度和速度要求。该研究的主要目的是开发一种背景校准技术，该技术将使带开环残差放大器的二级流水线ADC的设计。这项技术及其变型可以潜在地消除流水线ADC中对高增益放大器的需求，这对于现代细线CMOS技术中的高性能ADC设计尤为重要。建议和演示。所提出的双开关架构消除了保持模式馈通。因此，SHA在高达奈奎斯特速率的输入频率下保持线性。

著录项

  • 作者

    Dinc, Huseyin.;

  • 作者单位

    Georgia Institute of Technology.;

  • 授予单位 Georgia Institute of Technology.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2011
  • 页码 210 p.
  • 总页数 210
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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