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首页> 外文学位 >Analog integrated circuit design in ultra-thin oxide CMOS technologies with significant direct tunneling-induced gate current.
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Analog integrated circuit design in ultra-thin oxide CMOS technologies with significant direct tunneling-induced gate current.

机译：超薄氧化物CMOS技术中的模拟集成电路设计，具有显着的直接隧穿感应栅极电流。

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摘要

The ability to do mixed-signal IC design in a CMOS technology has been a driving force for manufacturing personal mobile electronic products such as cellular phones, digital audio players, and personal digital assistants. As CMOS has moved to ultra-thin oxide technologies, where oxide thicknesses are less than 3 nm, this type of design has been threatened by the direct tunneling of carriers though the gate oxide. This type of tunneling, which increases exponentially with decreasing oxide thickness, is a source of MOSFET gate current. Its existence invalidates the simplifying design assumption of infinite gate resistance. Its problems are typically avoided by switching to a high-kappa/metal gate technology or by including a second thick(er) oxide transistor. Both of these solutions come with undesirable increases in cost due to extra mask and processing steps. Furthermore, digital circuit solutions to the problems created by direct tunneling are available, while analog circuit solutions are not. Therefore, it is desirable that analog circuit solutions exist that allow the design of mixed-signal circuits with ultra-thin oxide MOSFETs. This work presents a methodology that develops these solutions as a less costly alternative to high-kappa/metal gate technologies or thick(er) oxide transistors. The solutions focus on transistor sizing, DC biasing, and the design of current mirrors and differential amplifiers. They attempt to minimize, balance, and cancel the negative effects of direct tunneling on analog design in traditional (non-high-kappa/metal gate) ultra-thin oxide CMOS technologies. They require only ultra-thin oxide devices and are investigated in a 65 nm CMOS technology with a nominal VDD of 1 V and a physical oxide thickness of 1.25 nm. A sub-1 V bandgap voltage reference that requires only ultra-thin oxide MOSFETs is presented ( TC = 251.0 ppm/°C). It utilizes the developed methodology and illustrates that it is capable of suppressing the negative effects of direct tunneling. Its performance is compared to a thick-oxide voltage reference as a means of demonstrating that ultra-thin oxide MOSFETs can be used to build the analog component of a mixed-signal system.
机译：以CMOS技术进行混合信号IC设计的能力一直是制造个人移动电子产品（如蜂窝电话，数字音频播放器和个人数字助理）的动力。随着CMOS转向氧化物厚度小于3 nm的超薄氧化物技术，这种类型的设计受到了载流子通过栅极氧化物直接隧穿的威胁。这种隧穿随着氧化物厚度的减小呈指数增长，是MOSFET栅极电流的来源。它的存在使无限门电阻的简化设计假设无效。通常可以通过切换到高kappa /金属栅极技术或通过包括第二个较厚的（较）氧化物晶体管来避免其问题。由于额外的掩模和处理步骤，这两种解决方案都带来不希望的成本增加。此外，可提供针对直接隧道技术所产生问题的数字电路解决方案，而无法提供模拟电路解决方案。因此，希望存在一种模拟电路解决方案，该解决方案允许设计具有超薄氧化物MOSFET的混合信号电路。这项工作提出了一种开发这些解决方案的方法，以作为高kappa /金属栅极技术或较厚（较）氧化物晶体管的低成本替代方案。这些解决方案专注于晶体管尺寸确定，直流偏置以及电流镜和差分放大器的设计。他们试图最大程度地减少，平衡和消除直接隧穿对传统（非高kappa /金属栅极）超薄氧化物CMOS技术中的模拟设计的负面影响。它们仅需要超薄氧化物器件，并且在65 nm CMOS技术中进行了研究，标称VDD为1 V，物理氧化物厚度为1.25 nm。提出了一种仅需超薄氧化物MOSFET的低于1 V的带隙基准电压（TC = 251.0 ppm /°C）。它利用了开发的方法并说明了它能够抑制直接隧穿的负面影响。将其性能与厚氧化物基准电压进行比较，以证明超薄氧化物MOSFET可用于构建混合信号系统的模拟组件。

著录项

  • 作者

    Bohannon, Eric.;

  • 作者单位

    Rochester Institute of Technology.;

  • 授予单位 Rochester Institute of Technology.;
  • 学科 Engineering General.;Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2011
  • 页码 203 p.
  • 总页数 203
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 公共建筑;
  • 关键词

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